Preliminary Information
MT9173/74
If the scramblers power up with all zeros in them,
they are not capable of randomizing all-zeros data
sequence. This increases the correlation between
the transmit and receive data which may cause loss
of convergence in the echo canceller and high bit
error rates.
Applications
Typical connection diagrams are shown in Figures 13
and 14 for the DN mode as a MASTER and SLAVE,
respectively. LOUT is connected to the coupling
transformer through a resistor R2 and capacitors C2
and C2’ to match the line characteristic impedance.
Suggested values of R2, C2 and C2’ for 80 and 160
kbit/s operation are provided in Figures 13 and 14.
Overvoltage protection is provided by R1, D1 and
D2. C1 is present to properly bias the received line
signal for the LIN input. A 2:1 coupling transformer is
used to couple to the line with a secondary center
tap for optional phantom power feed. Varistors have
been shown for surge protection against such things
as lightning strikes.
In DN mode the insertion of the SYNC pattern will
provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not
inserted. For this reason, at least on ”1” must be fed
into the DNIC on power up to ensure that the
scramblers will randomize any subsequent all-zeros
sequence.
C2’ = 1.5 nF
For 80 kbit/s: C2’ = 3.3 nF
+5V
MT9173/74
C2 = 22 nF
DSTi
D1 = D2 = MUR405
DV Port ST-BUS
{
DSTo
L
OUT
CDSTi
CDSTo
F0
2 : 1
D2
CD Port ST-BUS
Master Clocks
{
{
R2 = 390Ω
R1 = 47Ω
Line Feed
Voltage
68 Volts
(Typ)
C4
L
IN
1.0 µF
2.5 Joules
0.02 Watt
MS0
MS1
MS2
Mode Select
Lines
OSC1
D.C. coupled,
Frequency locked
10.24 MHz clock.
Refer to AC Electrical
Characteristics
Clock Timing
0.33 µF
OSC2
F0o
NC
+5V
V
V
Ref
Bias
C1 = 0.33 µF
0.33 µF
DN Mode.
RxSB
To Time
Measurement
Circuitry
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L ≈ V
To Next DNIC
IN
Bias
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
C2’ = 1.5 nF
For 80 kbit/s: C2’ = 3.3 nF
+5V
MT9173/74
DSTi
C2 = 22 nF
D1 = D2 = MUR405
DV Port ST-BUS
{
{
{
DSTo
L
OUT
CDSTi
CDSTo
F0
2:1
D2
CD Port ST-BUS
Master Clocks
R2 = 390Ω
R1 = 47Ω
C4
L
IN
1.0 µF
68 Volts
(Typ)
Supply
MS0
MS1
MS2
Mode Select
Lines
2.5 Joules
0.02 Watt
OSC1
OSC2
10.24 MHz XTAL
C3=33pF=C4
0.33 µF
+5V
V
Ref
V
Bias
0.33 µF
C1 = 0.33 µF
RxSB
To hardware
SYNC
Indicator
(optional)
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L ≈ V
IN
Bias
Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s
9-151
MITEL [ MITEL NETWORKS CORPORATION ]
