MT9173/74
Preliminary Information
t
t
C4W
C4P
2.0V
C4
0.8V
t
t
F0H
t
F0S
C4W
t
F0W
2.0V
F0
0.8V
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
2.0V
0.8V
C4
Φ
J
C
3.0V
2.0V
OSC1
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
AC Electrical Characteristics† - Clock Timing - MOD Mode (Figure 18)
80 kbit/s
160 kbit/s
Test
Conditions
Characteristics
Sym
Units
Min Typ* Max Min Typ* Max
1 TCK/RCK Clock Period
tCP
tCW
12.5
6.25
20
6.25
3.125
20
µs
µs
ns
µs
µs
µs
µs
2
3
TCK/RCK Clock Width
tCT
CL=40pF
TCK/RCK Clock Transition Time
tCLDS
tCLDH
tCLDW
tCLDP
3.125
3.125
6.05
8xtCP
1.56
1.56
2.925
8xtCP
4 CLD to TCK Setup Time
5 CLD to TCK Hold Time
6 CLD Width Low
7 CLD Period
† Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.
t
CP
t
CT
t
CW
2.4V
0.4V
RCK
TCK
t
CP
2.4V
0.4V
t
t
CLDH
CLDS
t
CW
t
CT
t
CLDW
2.4V
0.4V
CLD
Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the
DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D output
o
and may be skewed with respect to TCK due to end-to-end delay.
Note 2: At the slave end TCK is phase locked to RCK.
o
The rising edge of TCK will lead the rising edge of RCK by approximately 90 .
Figure 18 - RCK, TCK & CLD Timing For MOD Mode
9-154
MITEL [ MITEL NETWORKS CORPORATION ]
