Preliminary Information
MT9173/74
0
1
2
3
4
5
6
7
SYNC
CHQual
Rx HK
Future Functionality
ID
Status
Name
SYNC
Function
Register
0
Synchronization - When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
1-2
CHQual Channel Quality - These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
3
4-6
7
Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end.
Future Future Functionality. These bits return Logic 1 when read.
ID
This bit provides a hardware identifier for the DNIC revision. The MT9173/74 will
return a logic “0” for this bit.
Table 6. Status Register
channel boundaries of the data stream as shown in
Figure 8.
for the line by limiting the spectral content from
0.2fBaud to 1.6fBaud and on to a line driver where it is
made available to be put onto the line biased at VBias
.
The resulting transmit signal will have a distributed
spectrum with a peak at 3/4fBaud. The transmit signal
(LOUT) may be disabled by holding the LOUT DIS pin
high or by writing DLO (bit 6) of the Diagnostics
Register to logic “1”. When disabled, LOUT is forced
to the VBias level. LOUT DIS has an internal pull-down
to allow this pin to be left not connected in
applications where this function is not required. The
receive signal is the above transmit signal
superimposed on the signal from the remote end and
any reflections or delayed symbols of the near end
signal.
Line Port (LIN, LOUT
)
The line interface is made up of LOUT and LIN with
LOUT driving the transmit signal onto the line and LIN
receiving the composite transmit and receive signal
from the line. The line code used in the DNIC is
Biphase and is shown in Figure 10. The scrambled
NRZ data is differentially encoded meaning the
previous differential encoded output is XOR’d with
the current data bit which produces the current
output. This is then biphase encoded where
transitions occur midway through the bit cell with a
negative going transition indicating a logic "0" and a
positive going transition indicating a logic "1".
The frame format of the transmit data on the line is
shown in Figures 11 and 12 for the DN mode at 80
and 160 kbit/s. At 80 kbit/s a SYNC bit for frame
recovery, one bit of the D-channel and the B1-
channel are transmitted. At 160 kbit/s a SYNC bit,
the HK bit, two bits of the D-channel and both B1 and
B2 channels are transmitted.
There are some major reasons for using a biphase
line code. The power density is concentrated in a
spectral region that minimizes dispersion and
differential attenuation. This can shorten the line
response and reduce the intersymbol interference
which are critical for adaptive echo cancellation.
There are regular zero crossings halfway through
every bit cell or baud which allows simple clock
extraction at the receiving end. There is no D.C.
content in the code so that phantom power feed may
be applied to the line and simple transformer
coupling may be used with no effect on the data. It is
bipolar, making data reception simple and providing
a high signal to noise ratio. The signal is then passed
through a bandpass filter which conditions the signal
If the DINB bit of the Control Register is set, the
entire D-channel is transmitted during the B1-
channel timeslot. In MOD mode the SYNC, HK and
D-channel bits are not transmitted or received but
rather a continuous data stream at 80 or 160 kbit/s is
present. No frame recovery information is present on
the line in MOD mode.
9-149
MITEL [ MITEL NETWORKS CORPORATION ]
