Preliminary Information
MT9173/74
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated.
SS
Characteristics
Input Voltage
Sym
Min Typ* Max Units
Test Conditions
1
2
(LIN)
(LIN)
VIN
ZIN
5.0
Vpp
kΩ
Input Impedance
20
fBaud=160 kHz
I
N
3
Crystal/Clock Frequency
fC
10.24
0
MHz
ppm
%
4
P Crystal/Clock Tolerance
U
T
S
TC
-100
40
+100
60
➀
5a
5b
Crystal/Clock Duty Cycle
Crystal/Clock Duty Cycle
DCC
DCC
50
Normal temp. & VDD
➀
45
50
55
%
Recommended at max./
min. temp. & VDD
6
7
8
Crystal/Clock Loading
CL
Co
33
8
50
pF
pF
From OSC1 & OSC2 to VSS.
Output Capacitance
(LOUT
(LOUT
)
O
U
T
P
U
T
Load Resistance
)
RLout
500
100
Ω
kΩ
(VBias, VRef
)
9
Load Capacitance
Output Voltage
(LOUT
)
CLout
20
pF
µF
Capacitance to VBias.
(VBias, VRef
)
0.1
3.2
S
10
(LOUT
)
Vo
4.3
4.6
Vpp RLout = 500Ω, CLout = 20pF
† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
➀ Duty cycle is measured at V /2 volts.
DD
.
AC Electrical Characteristics† - Clock Timing - DN Mode (Figures 16 & 17)
Characteristics
C4 Clock Period
Sym
Min
Typ*
Max
Units
Test Conditions
1
2
3
4
5
6
tC4P
tC4W
tF0S
tF0H
tF0W
JC
244
122
ns
ns
ns
ns
ns
ns
C4 Clock Width High or Low
Frame Pulse Setup Time
Frame Pulse Hold Time
Frame Pulse Width
In Master Mode - Note 1
50
50
244
10.24 MHz Clock Jitter (wrt C4)
±15
Note 2
† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes: 1)
2)
When operating as a SLAVE the C4 clock has a 40% duty cycle.
When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F =2.5xf ). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from
C
C4
0 ns to t
. However, the relative jitter must be less than J (see Figure 17).
C4P
C
F0
C4
ST-BUS
Channel 31 Channel 0 Channel 0
BIT CELLS
Bit 0
Bit 7
Bit 6
Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams
9-153
MITEL [ MITEL NETWORKS CORPORATION ]
