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MT9092 参数 Datasheet PDF下载

MT9092图片预览
型号: MT9092
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS ST- BUS⑩系列数字电话与HDLC ( HPhone - II ) [ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II)]
分类和应用: 电话
文件页数/大小: 42 页 / 484 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9092  
General Control Register  
ADDRESS = 0Fh WRITE/READ VERIFY  
Power Reset Value  
Side  
A/µ  
Rx  
A/µ  
MIC  
A/µ  
NCT  
EN  
Sign-Mag/  
CCITT  
DATA  
RST  
A/µ  
0000 0000  
SEL  
7
6
5
4
3
2
1
0
RST  
Active high reset. Performs the same function as PWRST but does not affect the microport or the watchdog circuits.  
To remove this reset a PWRST must occur or this bit must be written low.  
DATASEL  
When high, the microport transmit and receive are performed on separate pins. DATA1 is receive while DATA2 is  
transmit. When low, the microport conforms to Intel MCS-51 mode 0 specifications; DATA1 is a bi-directional  
(transmit/receive) serial data pin while DATA2 is internally disconnected and tri-stated.  
A/µ  
When high, A-Law (de)coding is selected. When low, µ-Law (de)coding is selected.  
Sign-mag/CCITT When high, sign-magnitude bit coding is selected, When low, true CCITT PCM coding is selected.  
RxA/µ  
When high, the receiver driver nominal gain is set at -9.7 dB. When low this driver nominal gain is set at -12.3 dB.  
MICA/µ  
When high, the transmit amplifier nominal gain is set at 15.4 dB. When low this amplifier nominal gain is set at 6.1  
dB.  
SIDEA/µ  
When high, the side-tone nominal gain is set at -18.8 dB. When low this nominal gain is set at -11 dB.  
NCT EN  
When high, the new call tone generator output from the DSP is selected as the source for the loudspeaker path.  
When low, the CODEC output is selected for the loudspeaker path. Note that SPKR EN must also be set high for  
new call tone to function.  
ADDRESS 10h is RESERVED  
Watchdog Register  
ADDRESS = 11h WRITE  
Power Reset Value  
XXX0 1010  
-
-
-
W
W
W
W
W
0
4
3
2
1
7
6
5
4
3
2
1
0
WATCHDOG RESET WORD - XXX01010  
LCD Segment Enable Register 1  
ADDRESS = 12h WRITE/READ VERIFY  
Power Reset Value  
0000 0000  
SC  
7
SC  
6
SC  
5
SC  
4
SC  
3
SC  
2
SC  
1
SC  
0
8
7
6
5
4
3
2
1
Twelve segment control bits used for the LCD outputs. When high the respective segment is on. When low the respective segment is  
off.  
LCD Segment Enable Register 2  
ADDRESS = 13h WRITE/READ VERIFY  
Power Reset Value  
XXXX 0000  
-
-
-
SC  
3
SC  
2
SC  
1
SC  
-
12  
11  
10  
9
7
6
5
4
0
Twelve segment control bits used for the LCD outputs. When high the respective segment is on. When low the respective segment is  
off.  
Note: Bits marked "-" are reserved bits and should be written with logic "0".  
7-27  
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