MT9092
C-Channel Register
ADDRESS = 14h WRITE/READ
Power Reset Value
Write = 1111 1111
Read = Not Applicable
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
Micro-port access to the ST-BUS C-Channel information.
Timing Control Register
ADDRESS = 15h WRITE/READ VERIFY
Power Reset Value
XX0X 0000
-
-
-
-
CH EN CH EN CH EN
CH EN
3
2
1
0
7
6
5
4
3
2
1
0
All bits active high:
Ch2EN and Ch3EN
Channels 2 and 3 are the B1 and B2 channels, respectively. PCM associated with the DSP, Filter/CODEC and trans-
ducer audio paths is conveyed in one of these channels as selected in the timing control register.
Transmit B1 and B2 data on DSTo
When high PCM from the Filter/CODEC and DSP is transmitted on DSTo in the associated channel. When low
DSTo is forced to logic 0 for the corresponding timeslot. If both Ch2EN and Ch3EN are enabled, data defaults to
channel 2.
Receive B1 and B2 data on DSTi
When enabled PCM from DSTi is routed to the DSP and Filter/CODEC in the associated channel. If both Ch2EN
and Ch3EN are enabled, data input defaults to channel 2.
Ch1EN
Ch0EN
Channel 1 conveys the control/status information for the layer 1 transceiver. The full 64kb/s bandwidth is available and
is assigned according to which transceiver is being used. Consult the data sheets for the transceiver selected. When
high register data is transmitted on DSTo. When low this timeslot is tri-stated on DSTo. Receive C-Channel data (DSTi)
is always routed to the register regardless of this control bit's logic state.
Channel 0 conveys the D-Channel HDLC information. Since this function is dedicated to 16kb/s operation, only the first
Loop-back Register
LBio
ADDRESS = 16h WRITE/READ VERIFY
Power Reset Value
X00X XXXX
-
LBoi
5
-
-
-
-
-
7
6
4
3
2
1
0
LBio
LBoi
Active high enables data from the ST-BUS input to be looped back to the ST-BUS output directly at the pins. The DSTo tri-
state driver must also be enabled using one of the channel enable signals.
Active high enables data from ST-BUS output to be looped back to the ST-BUS input directly at the pins.
ADDRESS 17h-1Ch are RESERVED
Note: Bits marked "-" are reserved bits and should be written with logic "0".
7-28
MITEL [ MITEL NETWORKS CORPORATION ]
