MT90810
Preliminary Information
t
AH
AD[0:7]
Read Data
Add
t
AS
ALE
CS
t
DOFF
t
ACC
RD
t
t
RDY
DAC
RDY
Notes:
RDY is only driven low during memory (slow) cyles.
tDOFF is measured from either CS or RD going high, whichever is later.
Figure 22 - Intel Multiplexed Bus Timing for Read Cycle (ALE is active)
t
AH
AD[0:7]
ALE
Add
AS
Write Data
t
t
DH
CS
t
DAC
t
ACC
WR
t
RDY
RDY
Notes:
RDY is only driven low during memory (slow cyles).
tDH is measured from either CS or WR going high, whichever is earlier.
Figure 23 - Intel Multiplexed Bus Timing for Write Cycle (ALE is active)
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