MT9076
Preliminary Information
Bit
Name
Functional Description
7
- --
Unused.
These bits select the RXFF (Rx FIFO Full) interrupt threshold level:
6-4
RFFS2-0
RFFS2
RFFS1
RFFS0
RX FIFO Full Interrupt threshold Level.
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64
72
0
0
80
0
88
1
96
1
104
112
120
1
1
3
- --
Unused.
2-0
TFLS2-0
These bits select the TXFL (Tx FIFO Low) interrupt threshold level:
TFLS2
TFLS1
TFLS0
TX FIFO Low Interrupt threshold Level.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
24
32
40
48
56
64
Table 172 - HDLC Control Register 4
(Page B, C & D, Address 1EH)
Bit
Name
Functional Description
7-0
TxCNT15-8 Extended Transmit Byte Count Register. This register, along with the Transmit Byte
Count Register indicates the length of the packet about to be transmitted. Values
programmed into this register are not internally updated until the next write to the Low
Transmit Byte Count Register. When the internal counter decrements to one, the next
write to the Tx FIFO will be tagged as an end of packet byte. The counter decrements at
the end of the write to the Tx FIFO. If the Cycle bit of Control Register 2 is set high, the
counter will cycle through the programmed value continuously.
Table 173 - Extended Transmit Byte Count Register
(Page B,C & D, Address 1FH)
136
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