MT9076
Preliminary Information
Bit
Name
Functional Description
7-4
3
- -
These bits are reserved.
RxCLK
Receive Clock. This bit represents the receiver clock generated after the RXEN
control bit, but before zero deletion is considered.
2
1
TxCLK
VCRC
Transmit Clock. This bit represents the transmit clock generated after the TXEN
control bit, but before zero insertion is considered.
Valid CRC. This is the CRC recognition status bit for the receiver. Data is clocked
into the register and then this bit is monitored to see if comparison was successful
(bit will be high).
0
VADDR
Valid Address. This is the address recognition status bit for the receiver. Data is
clocked into the Address Recognition Register and then this bit is monitored to see
if comparison was successful (bit will be high).
Table 170 - HDLC Test Status Register
(Page B,C & D, Address 1CH)
134
MITEL [ MITEL NETWORKS CORPORATION ]
