Preliminary Information
MT9076
Bit
Name
Functional Description
7
6
- - -
Unused.
JFC
Jitter Attenuator FIFO Centre. When this bit is toggled the read pointer on the jitter
attenuator shall be centered. During this centering the jitter on the JA outputs is increased
by 0.0625 U.I.
5 - 3 JFD2-JFD0 Jitter Attenuator FIFO Depth Control Bits. These bits determine the depths of the jitter
attenuator FIFO as shown below:
JFD2
JFD1
JFD0
Depth
16
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32
48
64
80
96
112
128
2
JACL
- - -
Jitter Attenuator FIFO Clear Bit. If one, the Jitter Attenuator, its FIFO and status are reset.
The status registers will identify the FIFO as being empty. However, the actual bit values of
the data in the JA FIFO will not be reset.
1 - 0
Unused.
Table 106 - Jitter Attenuation Control Word
(Page 2, Address 13H) (E1)
Bit
Name
Functional Description
7-0
EHT7-0
Equalizer High Threshold. These bits set the highest possible binary count tolerable
coming out of the equalized signal peak detector before a lower level of equalization is
selected. This register is only used when A/D based automatic equalization is selected using
the Rx LIU Control Word. The recommended value to program is 10111011.
Table 107 - Equalizer High Threshold
(Page 2, Address 16H) (E1)
Bit
Name
Functional Description
7-0
ELT7-0
Equalizer Low Threshold. These bits set the lowest possible binary count tolerable coming
out of the equalized signal peak detector before a higher level of equalization is selected.
This register is only used when A/D based automatic equalization is selected using the Rx
LIU Control Word. The recommended value to program is 00110000.
Table 108 - Equalizer Low Threshold
(Page 2, Address 17H) (E1)
105
MITEL [ MITEL NETWORKS CORPORATION ]
