Preliminary Information
MT9076
Bit
Name
Functional Description
7
FEOM
Frame Alignment Signal Error Counter Overflow Interrupt Mask. When unmasked an
interrupt is initiated when the frame alignment signal error counter overflows. If 1 -
unmasked, 0 - masked.
6
CRCOIM
CRC-4 Error Counter Overflow Interrupt Mask. When unmasked an interrupt is initiated
when the CRC-4 error counter overflows. If 1 - unmasked, 0 - masked.
5
4
- - -
Unused.
EBOIM
Receive E-bit Counter Overflow Interrupt Mask. When unmasked an interrupt is
initiated when the E-bit error counter overflows. If 1 - unmasked, 0 - masked.
3
2
1
0
LCVCOM Line Code Violation Counter Overflow Interrupt Mask. When unmasked (LCVO = 1),
an interrupt is initiated when the line code violation error counter changes form FFFFH to
0H. If 1- unmasked 0 - masked.
PRBSOM PRBS Counter Overflow Interrupt Mask. When unmasked (PRBSO = 1), an interrupt is
initiated on overflow of PRBS counter (page 04H, address 10H) from FFH to 0H. If 1-
unmasked 0 - masked.
PRBSMFOM PRBS MultiFrame Counter Overflow Interrupt Mask. When unmasked an interrupt will
be generated whenever the multiframe counter attached to the PRBS error counter
overflows. If 1- unmasked 0 - masked.
SaIM
Sa Bits Interrupt Masks. When unmasked an interrupt will be triggered by either a
change of state of any of the received Sa bits Sa5, Sa6, Sa7 or Sa8 (SaBorNi = 1) or a
change of state of any of the received Sa nibbles (SaBorNi = 0). The control bit SaBorNi is
located in page 1 address 12H bit 4. If 1- unmasked 0 - masked.
Table 100 - Interrupt Mask Word Two (E1)
(Page 1, Address 1DH)
101
MITEL [ MITEL NETWORKS CORPORATION ]
