MT9076
Preliminary Information
Bit Name
Functional Description
7
RST
Software reset. Setting this bit is equivalent to performing a hardware reset. All counters are
cleared and the control registers are set to their default values. This control bit is internally
cleared after the reset operation is complete.
6
5
SPND Suspend Interrupts. If one, the IRQ output will be in a high-impedance state and all interrupts
will be ignored. If zero, the IRQ output will function normally.
INTA
Interrupt Acknowledge. Setting this pin clears all interrupts and forces the IRQ pin into high
impedance. The control bit itself is then internally cleared.
4
3
CNTCLR Counter Clear. If one, all status error counters are cleared and held low.
SAMPLE One Second Sample. Setting this bit causes the error counters (change of frame alignment, loss
of frame alignment, lcv errors, crc errors, severely errored frame events and multiframes out of
sync) to be updated on one second intervals coincident with the one second timer (status page 3
address 12H bit 7).
2
OOFP Out of Frame Pause. If set high, this bit will suspend operation of the Line Code VIolation
Counter during an out - of - frame condition; upon achieving terminal frame synchronization the
counter will resume normal operation. If set low, the Line Code Violation counter will continue to
count errors even if terminal frame synchronization is lost.
1
0
--
Reserved. Set to zero for normal operation.
D20
Double20. Set to zero for normal operation. Set high to double clock speed in the HDLC,
speeding up microport accesses from 160ns between consecutive reads/writes to 80ns between
consecutive reads/writes.
Table 30 - Reset Control Word (T1)
(Page 1, Address 1AH)
64
MITEL [ MITEL NETWORKS CORPORATION ]
