MT9076
Preliminary Information
10.2.1 Notes for Synchronization State Diagram (Figure 16)
1) The basic frame alignment, signaling multiframe alignment, and CRC-4 multiframe alignment functions
operate in parallel and are independent.
2) The receive channel associated signaling bits and signaling multiframe alignment bit will be frozen when
multiframe alignment is lost.
3) Manual re-framing of the receive basic frame alignment and signaling multiframe alignment functions can be
performed at any time.
4) The transmit RAI bit will be one until basic frame alignment is established, then it will be zero.
5) E-bits can be optionally set to zero until the equipment interworking relationship is established. When this
has been determined one of the following will take place:
a) CRC-to-non-CRC operation - E-bits = 0,
b) CRC-to-CRC operation - E-bits as per G.704 and I.431.
6) All manual re-frames and new basic frame alignment searches start after the current frame alignment signal
position.
7) After basic frame alignment has been achieved, loss of frame alignment will occur any time three
consecutive incorrect basic frame alignment signals are received. Loss of basic frame alignment will reset
the complete framing algorithm.
8) When CRC-4 multiframing has been achieved, the primary basic frame alignment and resulting multiframe
alignment will be adjusted to the basic frame alignment determined during CRC-4 synchronization.
Therefore, the primary basic frame alignment will not be updated during the CRC-4 multiframing search, but
will be updated when the CRC-4 multiframing search is complete.
10.3
Reframe
10.3.1 E1 Mode
The MT9076 will automatically force a reframe, if three consecutive frame alignment patterns or three
consecutive non-frame alignment bits are in error.
10.3.2 T1 Mode
The MT9076 will automatically force a reframe if the framing bit error density exceeds the threshold
programmed by control bits RS1-0 (Framing Mode Select Word page 1H, address 10H). RS1 = RS0 = 0 forces
a reframe for 2 errors out of a sliding window of 4 framing bits. RS1 = 0, RS0 = 1 forces a reframe with 2 errors
out of 5. RS1 = 1, RS0 = 0 forces a reframe with 2 errors out of 6. RS1 = RS0 = 1 disables the automatic
reframe.
In ESF mode, all framing bits are checked. In D4 mode, either Ft bits only (if control bit 2 - FSI - of Framing
Mode Select Register is set low) or Ft and Fs bits are checked (FSI set high). If the D4 secondary yellow alarm
is enabled (control bit 1 - D4SECY of Transmit Alarm Control Word page 1H, address 11H) then the Fs bit of
frame 12 is not verified for the loss of frame circuit.
In E1 or T1 mode, receive transparent mode (selected when bit 3 page 1 address 12H is high) no reframing is
forced by the device.
The user may initiate a software reframe at any time by setting bit 1, page 1, address 10H high (ReFR). Once
the circuit has commenced reframing the signaling bits are frozen until multiframe synchronization has been
achieved.
11.0 MT9076 Channel Signaling
11.1
Channel Signaling in T1 Mode
In T1 mode, when control bit RBEn (page 1H, address 14H) is low the MT9076 will insert ABCD or AB
signaling bits into bit 8 of every transmit DS0 channel every 6th frame. The AB or ABCD signaling bits from
received frames 6 and 12 (AB) or from frames 6, 12, 18 and 24 (ABCD) will be loaded into an internal storage
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MITEL [ MITEL NETWORKS CORPORATION ]
