MT9076
Preliminary Information
There is one interrupt associated with the Out of Frame counter. A counter overflow interrupt may be enabled
by setting control bit OOFO high - bit 5 of Interrupt Mask Word Two (page 1H, address 1DH).
13.2.3 Multiframes out of Sync Counter (MFOOF7-MFOOF0)
This eight bit counter MFOOF7 - MFOOF0 is located on page 4 address 15H, and is incremented once per
multiframe (1.5 ms for D4 and 3 ms for ESF) during the time that the framer is out of terminal frame
synchronization.
There is a maskable interrupt associated with the measurement. A counter overflow interrupt may be enabled
by setting control bit MFOOFO high - bit 1 of Interrupt Mask Word Two (page 1H, address 1DH).
13.2.4 CRC-6 Error Counter (CC15-0)
CRC-6 errors are recorded by this counter for ESF links. This 16 bit counter is located on page 4, addresses
18H and 19H.
There are two maskable interrupts associated with the CRC error measurement. A single error may generate
an interrupt (enable by setting CRCI high - bit 6 of the Interrupt Mask Word One, page 1H, address 1CH). A
counter overflow interrupt may be enabled by setting control bit CRCO high - bit 6 of Interrupt Mask Word Two
(page 1H, address 1DH).
13.2.5 Line Code Violation Error Counter (LCV15-LCV0)
If the control bit EXZ (page 1 address 12H bit 5) is set low, the line code violation error counter will count
bipolar violations that are not part of B8ZS encoding. If the control bit EXZ (page 1 address 12H bit 5) is set
high, the line code violation error counter will count both bipolar violations that are not part of B8ZS encoding
and each occurance of excess zeros (more than 7 successive zeros in a received B8ZS encoded data stream
and more than 15 successive zeros in a non-B8ZS encoded stream). This counter LCV15-LCV0 is 16 bits long
(page 4H, addresses 16H and 17H) and is incremented once for every line code violation received. It should be
noted that when presetting or clearing the LCV error counter, the least significant LCV counter address should
be written to before the most significant location. This counter will suspend operation when terminal frame
synchronization is lost if the control bit OOFP is set (bit 2, address 1AH - Reset Control Word).
There are two maskable interrupts associated with the line code violation error measurement. A single error
may generate an interrupt (enable by setting LCVI high - bit 3 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be enabled by setting control bit LCVO high - bit 3 of Interrupt
Mask Word Two (page 1H, address 1DH).
13.2.6 PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS comparison; one for errors and one for time. Any errors that
are detected in the receive PRBS will increment the PRBS Error Rate Counter of page 04H, address 10H.
Writes to this counter will clear an 8 bit counter, PSM7-0 (page 01H, address 11H) which counts receive CRC
multiframes. A maskable PRBS counter overflow (PRBSO) interrupt (page 1, address 1DH) is associated with
this counter.
13.2.7 CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC multiframes. It can be directly loaded via the microport. The counter
will also be automatically cleared in the event that the PRBS error counter is written to by the microport. This
counter is located on page 04H, address 11H.
13.3
13.4
E1 Counters
Errored FAS Counter (EFAS7-EFAS0)
An eight bit Frame Alignment Signal Error counter EFAS7 - EFAS0 is located on page 04H address 13H, and is
incremented once for every receive frame alignment signal that contains one or more errors.
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