MT9076
Preliminary Information
(i) It may free - run with the internal multiframe counters;
(ii) The multiframe counters may be reset with the external hardware pin TxMF. If this signal is not
synchronous with the current transmit frame count it may cause the far end to go temporarily out of sync.
(iii) Under software control (by setting the TxSYNC bit in page 01 address 12H) the transmit multiframe
counters will be synchronized to the framing pattern present in the overhead bits multiplexed into channel
31 bit 0 of the incoming 2.048 Mb/s digital stream DSTi. Note that the overhead bits extracted from the
receive signal are multiplexed into outgoing DSTo channel 31 bit 0.
(iv) In SLC - 96 mode the transmit frame counters synchronize to the framing pattern clocked in on the TXDL
input
Frame #
Ft
Fs
Signaling
1
2
1
0
0
1
1
1
0
3
0
1
0
1
0
4
5
6
A
B
7
8
9
10
11
12
Table 7 - D4 Superframe Structure(T1)
Frame #
FPS
FDL
CRC
Signaling
1
2
X
CB1
3
X
X
X
X
X
X
X
X
X
X
X
4
0
0
1
0
1
1
5
6
CB2
CB3
CB4
CB5
CB6
A
B
C
D
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Table 8 - ESF Superframe Structure (T1)
26
MITEL [ MITEL NETWORKS CORPORATION ]
