MT9075A
Preliminary Information
slots to the transmit PCM 30 time slots. Local time
slot loopback bit LTSL = 0 normal; LTSL = 1 activate,
will loop around DSTi time slots towards the DSTo
time slots.
MT9075A
DSTi
System
Tx
PCM30
DSTo
MT9075A
Tx
DSTi
b) Remote Loopback (RM Loop) - RTIP and RRING
to TTIP and TRING respectively at the PCM 30 side.
Bit RLBK = 0 normal; RLBK = 1 activate.
System
PCM30
Rx
DSTo
Error Counters
MT9075A
Tx
PCM30
Rx
The MT9075A has nine error counters, which can be
used for maintenance testing, an ongoing measure
of the quality of a PCM 30 link and to assist the
designer in meeting specifications such as ITU-T
I.431 and G.821. All counters can be preset or
cleared by writing to the appropriate locations. A
separate status page - “1 Second Status” on page
09H - latches the states of the following counters: E-
bit Error Counter, Errored Frame Alignment Signal
Counter, Bipolar Violation Counter and CRC Error
Counter on a one second interval, coincident with
the one second status bit.
System
DSTo
c) ST-BUS Loopback (ST Loop) - DSTi to DSTo at
the system side. Bit SLBK = 0 normal; SLBK = 1
activate.
MT9075A
Tx
PCM30
DSTi
System
DSTo
Associated with each counter is a maskable event
occurrence interrupt and
a
maskable counter
d) Payload Loopback (PL Loop) - RTIP and RRING
to TTIP and TRING respectively at the system side
with FAS and NFAS operating normally. Bit PLBK = 0
normal; PLBK = 1 activate. The payload loopback is
effectively a physical connection of DSTo to DSTi
within the MT9075A. Channel zero and the DL
originate at the point of loopback.
overflow interrupt. Overflow interrupts are useful
when cumulative error counts are being recorded.
For example, every time the frame error counter
overflow (FERO) interrupt occurs, 256 frame errors
have been received since the last FERO interrupt. All
counters are cleared and held low by programming
the counter clear bit (master control page 01H,
address 1AH, bit 2) high. Counter overflows set bits
in the counter overflow latch (page 04H, address
16H); this latch is cleared when read.
MT9075A
DSTi
System
DSTo
Tx
Rx
PCM30
The overflow reporting latch (page 04H, address
16H) contains a register whose bits are set when
individual counters overflow. These bits stay high
until the register is read.
e) Metallic Loopback (MT Loop) - The external
signals RTIP and RRING are isolated from the
receiver and the analog outputs TTIP and TRING are
internally connected to the receiver analog input. Bit
MLBK = 0 normal; MLBK = 1 activate.
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS
comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 01H, address 11H)
MT9075A
DSTi
System
DSTo
Tx
Rx
PCM30
which counts receive CRC-4 multiframes.
A
maskable PRBS counter overflow (PRBSO) interrupt
(page 1, address 19H) is associated with this
counter.
f) Local and Remote Time Slot Loopback. Remote
time slot loopback control bit RTSL = 0 normal; RTSL
= 1 activate, will loop around receive PCM 30 time
4-152
MITEL [ MITEL NETWORKS CORPORATION ]
