Preliminary Information
MT9075A
CRC Multiframe Counter for PRBS (PSM7-0)
Errored FAS Counter (EFAS7-EFAS0)
This eight bit counter counts receive CRC-4
multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.
An eight bit Frame Alignment Signal Error counter
EFAS7 - EFAS0 is located on page 04H address
1AH, and is incremented once for every receive
frame alignment signal that contains one or more
errors.
There are two maskable interrupts associated with
the frame alignment signal error measurement. FERI
(page 01H, address 1BH) is initiated when the least
significant bit of the errored frame alignment signal
counter toggles, and FERO (page 01H, address
1DH) is initiated when the counter changes from
FFH to 00H.
E-bit Counter (EC9-0)
E-bit errors are counted by the MT9075A in order to
support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
13H and 14H respectively. It is incremented by single
error events, with a maximum rate of twice per CRC-
4 multiframe.
Bipolar Violation Error Counter (BPV15-BPV0)
There are two maskable interrupts associated with
the E-bit error measurement. EBI (page 1, address
1CH) is initiated when the least significant bit of the
counter toggles, and EBO (page 01H, address 1DH)
is initiated when the counter overflows.
The bipolar violation error counter will count bipolar
violations or encoding errors that are not part of
HDB3 encoding. This counter BPV15-BPV0 is 16
bits long (page 04H, addresses 1DH and 1CH) and
is incremented once for every BPV error received. It
should be noted that when presetting or clearing the
BPV error counter, the least significant BPV counter
address should be written to before the most
significant location.
Jitter FIFO Counter (JFC7-0)
This is an eight bit counter that is incremented when
the FIFO read pointer comes within 4 words of an
underflow or overflow condition. During this time the
read clock will abruptly speed-up or slow-down to
avoid an overflow or underflow condition. This
counter is located on page 04H, address 15H.
There are two maskable interrupts associated with
the bipolar violation error measurement. BPVI (page
01H, address 1CH) is initiated when the least
significant bit of the BPV error counter toggles.
BPVO (page 01H, address 1BH) is initiated when the
counter changes from FFFFH to 0000H.
Loss of Synchronization Counter (LBF7-0)
CRC Error Counter (CC9-0)
This eight bit counter increments with each loss of
basic frame alignment. This programmable counter
is located on page 04H, address 17H.
CRC-4 errors are counted by the MT9075A in order
to support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
1EH and 1FH respectively. It is incremented by
single error events, which is a maximum rate of twice
per CRC-4 multiframe.
Bit Error Rate Counter (BR7-BR0)
An 8 bit Error Rate (BERT) counter BR7 - BR0 is
located on page 04H address 18H, and is
incremented once for every bit detected in error on
either the seven frame alignment signal bits.
There is a maskable interrupts associated with the
CRC error measurement. CRCI (page 01H, address
1CH) is initiated when the least significant bit of the
counter toggles, and CRCO (page 01H, address
1DH) is initiated when the counter overflows.
There are two maskable interrupts associated with
the bit error rate measurement. BERI (page 01H,
address 1CH) is initiated when the least significant
bit of the BERT counter (BR0) toggles, and BERO
(page 01H, address 1DH) is initiated when the BERT
counter value changes from FFH to 00H.
Error Insertion
Six types of error conditions can be inserted into the
transmit PCM 30 data stream through control bits,
which are located on page 02H, address 10H. These
error events include the bipolar violation errors
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