Preliminary Information
MT9075A
SYNC
CRCSYN
CRCIWK
Recommended Transmit RAI setting
Set transmit RAI continuously low.
0
0
1
0
0
0
0
1
1
1
1
0
x
1
0
This state cannot exist with AUTC set low.
Set transmit RAI continuously high.
Transmit a flickering (0 to 1 to 0) RAI every 8 milliseconds.
The link is a CRC to non CRC link. Set transmit RAI to the appropriate
stable state (usually low).
Table 4 - Transmit RAI setting for CRC to non CRC interworking with AUTC set low
There are two CRC multiframe alignment algorithm
options selected by the AUTC control bit (address
11H, page 01H). When AUTC is zero and CSYN is
zero, automatic CRC-to-non-CRC interworking is
selected, if CRC-4 multiframe alignment is not found
in 400 msec, the status bit CRCIWK (page 03H,
address 10H) is set low and no further attempt to
achieve CRC-4 synchronization is made as long as
which occurs in the most significant nibble of time
slot 16 of basic frame 0 of the CAS multiframe. Bit 6
of this time slot is the multiframe alarm bit (usually
designated Y). When CAS multiframing is acquired
on the receive side, the transmit Y-bit is zero; when
CAS multiframing is not acquired, the transmit Y-bit is
one. Bits 5, 7 and 8 (usually designated X) are spare
bits and are normally set to one if not used.
the
device
remains
in
terminal
frame
synchronization. When AUTC is one and CSYN is
zero, a reframe will be initiated every 8 msec if the
MT9075A achieves terminal frame synchronization,
but fails to achieve CRC-4 synchronization.
Time slot 16 of the remaining 15 basic frames of the
CAS multiframe (i.e., basic frames 1 to 15) are
reserved for the ABCD signalling bits for the 30
payload channels. The most significant nibbles are
reserved for channels 1 to 15 and the least
significant nibbles are reserved for channels 16 to
30. That is, time slot 16 of basic frame 1 has ABCD
for channel 1 and 16, time slot 16 of basic frame 2
has ABCD for channel 2 and 17, through to time slot
16 of basic frame 15 has ABCD for channel 15 and
30.
The control bit for transmit E bits (TE, bit 4 at
address 16H of page 01H) will have the same
function in both states of AUTC. That is, when CRC-4
synchronization is not achieved the state of the
transmit E-bits will be the same as the state of the TE
control bit. When CRC-4 synchronization is achieved
the transmit E-bits will function as per ITU-T G.704.
Table 4 outlines the recommended setting of the
TALM control bits of the MT9075A.
MT9075A Access and Control
Register Access
CAS Signalling Multiframing
The control and status of the MT9075A is achieved
through a non-multiplexed parallel microprocessor
port. The parallel port may be configured for
Motorola style control signals (by setting pin INT/
MOT low) or Intel style control signals (by setting pin
INT/MOT high).
The purpose of the signalling multiframing algorithm
is to provide a scheme that will allow the association
of a specific ABCD signalling nibble with the
appropriate PCM 30 channel. Time slot 16 is
reserved for the communication of Channel
Associated Signalling (CAS) information (i.e., ABCD
signalling bits for up to 30 channels). Refer to ITU-T
G.704 and G.732 for more details on CAS
multiframing requirements.
The controlling microprocessor gains access to
specific registers of the MT9075A through a two step
process. First, writing to the internal Command/
Address Register (CAR) selects one of the 18 pages
of control and status registers (CAR address: AC4 =
0, AC3-AC0 = don't care, CAR data D7 - D0 = page
number). Second, each page has a maximum of 16
registers that are addressed on a read or write to a
non-CAR address (non-CAR: address AC4 = 1, AC3-
AC0 = register address, D7-D0 = data). Once a page
A CAS signalling multiframe consists of 16 basic
frames (numbered 0 to 15), which results in a
multiframe repetition rate of 2 msec. It should be
noted that the boundaries of the signalling multiframe
may be completely distinct from those of the CRC-4
multiframe. CAS multiframe alignment is based on a
multiframe alignment signal (a 0000 bit sequence),
4-141
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