MT9074
Advance Information
Bit
Name
Functional Description
Bit Name
Functional Description
7
FERRO Errored Framing Alignment
Signal Counter Overflow
7
6
- - -
Unused
HDLC0I HDLC0 Interrupt. Whenever an
unmasked HDLC0 interrupt occurs.
This bit goes high. Reading this
register clears this bit.
Interrupt. When unmasked this
interrupt bit goes high whenever
the errored frame alignment signal
counter changes from FFH to 00H.
Reading this register clears this
bit.
5
4
HDLC1I HDLC1 Interrupt. Whenever an
unmasked HDLC1 interrupt occurs.
this bit goes high. Reading this
register clears this bit.
6
5
CRCO
CRC Error Counter Overflow
Interrupt. When unmasked this
interrupt bit goes high whenever
the CRC error counter changes
from FFH to 00H. Reading this
register clears this bit.
JAI
Jitter Attenuator Error Interrupt.
Whenever an unmasked JAI interrupt
occurs.
If jitter attenuator FIFO comes within
four bytes of an overflow or underflow,
this bit goes high. Reading this
register clears this bit.
FEBEO E-bit
Counter
Overflow
Interrupt. When unmasked this
interrupt bit goes high whenever
the E-bit counter changes from
FFH to 00H. Reading this register
clears this bit.
3
1SECI One Second Status Interrupt. When
unmasked this interrupt bit goes high
whenever the 1SEC status bit (page 3
address 12H bit 7) goes from low to
high. Reading this register clears this
bit.
4
3
- - -
Unused
BPVO
Bipolar
Overflow
Violation
Interrupt.
Counter
When
2
1
0
5SECI Five Second Status Interrupt. When
unmasked this interrupt bit goes high
whenever the 5 SEC status bit goes
from low to high. Reading this register
clears this bit.
unmasked this interrupt bit goes
high whenever the bipolar violation
counter changes from FFH to 00H.
Reading this register clears this
bit.
RCRI RCRI Interrupt. Whenever an
unmasked RCRI interrupt occurs. If
remote alarm and CRC error occur
this bit goes high. Reading this
register clears this bit.
2
1
PRBSO Pseudo Random Bit Sequence
Error Counter Overflow
Interrupt. When unmasked this
interrupt bit goes high whenever
the PRBS error counter changes
from FFH to 00H. Reading this
register clears this bit.
SIGI Signalling
unmasked this interrupt bit goes high
whenever change of state
Interrupt.
When
a
PRBSMFO Pseudo Random Bit Sequence
Multiframe Counter Overflow
Interrupt. When unmasked this
interrupt bit goes high whenever
the multiframe counter attached to
the PRBS error counter overflows.
FFH to 00H. 1 - unmasked, 0 -
masked.
(optionally debounced - see DBEn in
the Data Link, Signalling Control
Word) is detected in the signalling bits
(AB or ABCD) pattern. Reading this
register clears this bit.
Table 129 - Interrupt Word Three
(Page 4, Address 1EH) (E1)
0
- - -
Unused
Table 128 - Interrupt Word Two
(Page 4, Address 1DH) (E1)
92
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