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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9074  
Advance Information  
Bit Name  
Functional Description  
Bit  
Name  
Functional Description  
7
T1/E1  
T1/E1 mode selection. when this  
bit is zero, the device is in T1  
mode. When set high, the device  
is in E1 mode.  
7
RSV Reserved. Must be kept high for  
normal operation.  
6-4 RSV Reserved. Must be kept low for normal  
operation.  
6-5  
4
RSV  
Reserved. Must be kept at 0 for  
normal operation.  
3
CPL Custom Pulse Level. Setting this bit  
low enables the internal ROM values in  
generating the transmit pulses. The  
ROM is coded for different line  
terminations or build out, as specified  
in the LIU Control word. Setting this bit  
high disables the pre-programmed  
pulse templates. Each of the 4 phases  
that generate a mark derive their D/A  
LIUEn  
LIU Enable. Setting this bit low  
enables the internal LIU front-end.  
Setting this pin high disables the  
LIU. Digital inputs RXA and RXB  
are sampled by the rising edge of  
E1.5i (C1.50) to strobe in the  
received line data. Digital transmit  
data is clocked out of pins TXA  
and TXB with the rising edge of  
C1.5o  
coefficients  
from  
the  
values  
programmed in the CPW registers.  
2-0 RSV Reserved. Must be kept at 0 for normal  
3-2  
1
RSV  
Reserved. Must be kept at 0 for  
normal operation.  
operation.  
Table 39 - Custom Tx Pulse Enable  
(Page 2, Address 11H) (T1)  
ADSEQ Digital Milliwatt or Digital Test  
Sequence. If one, the Alaw digital  
milliwatt analog test sequence will  
be selected for those channels  
with per time slot control bits  
TTST, RRST set. If zero, a PRBS  
Bit Name  
Functional Description  
7
RSV Reserved. Must be kept low for normal  
generator  
/
detector will be  
operation.  
connected to channels with TTST,  
RRST respectively.  
6-0 CP6-0 Custom Pulse. These bits provide the  
capability for programming the  
0
RSV  
Reserved. Must be kept at 0 for  
normal operation.  
magnitude setting for the TTIP/TRING  
line driver A/D converter during the first  
phase of a mark. The greater the  
binary number loaded into the register,  
the greater the amplitude driven out.  
This feature is enabled when the  
control bit 3 - CPL of the Custom Tx  
Pulse Enable Register - address 11H  
of Page 2 is set high.  
Table 38 - Configuration Control Word  
(Page 2, Address 10H) (T1)  
Table 40 - Custom Pulse Word 1  
(Page 2, Address 1CH) (T1)  
52  
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