Advance Information
MT9074
Bit
Name
Functional Description
7
INTGEN
Interrupt Generated. Set to 1 when an interrupt (in conjunction with the Interrupt
Mask Register) has been generated by the HDLC. This is an asynchronous event.
It is reset when the interrupt Register is read.
6
Idle Chan
RQ9, RQ8
Idle Channel. Set to a 1 when an idle Channel state (15 or more ones) has been
detected at the receiver. This is an asynchronous event. On power reset, this may
be 1 if the clock (RXC) was not operating. Status becomes valid after the first 15
bits or the first zero is received.
5 - 4
Byte Status bits from RX FIFO. These bits determine the status of the byte to be
read from RX FIFO as follows:
RQ9 RQ8 Byte Status
0
0
1
1
0
1
0
1
Packet Byte
First Byte
Last byte of a good packet.
Last byte of a bad packet.
3 - 2
TxSTAT2-1
These bits determine the status of the TX FIFO as follows:
TxSTAT2 TxSTAT1 TX FIFO Status
0
0
0
1
TX FIFO full up to the selected status level or more.
The number of bytes in the TX FIFO has reached or
exceeded the selected interrupt threshold level.
TX FIFO empty.
1
1
0
1
The number of bytes in the TX FIFO is less than the
selected interrupt threshold level.
1 - 0
RxSTAT2 - 1 These bits determine the status of the RX FIFO as follows:
RxSTAT2 RxSTAT1 RX FIFO Status
0
0
0
1
RX FIFO empty
The number of bytes in the RX FIFO is less
than the interrupt threshold level.
RX FIFO full.
1
1
0
1
The number of bytes in the RX FIFO has reached or
exceeded the interrupt threshold level.
Table 145 - HDLC Status Register
(Page B & C Address 14H)
101
MITEL [ MITEL NETWORKS CORPORATION ]
