MT9074
Advance Information
Bit
Name
Functional Description
Bit
Name
Functional Description
2
Mark-Idle
When low, the transmitter will
be in an idle state. When high it
is in an interframe time fill state.
These two states will only occur
when the TX FIFO is empty.
7
ADREC
When high this bit will enable
address
recognition.
This
forces the receiver to recognize
only those packets having the
unique address as programmed
1
TR
When high this bit will enable
transparent mode. This will
perform the parallel to serial
conversion without inserting or
deleting zeros. No CRC bytes
are sent or monitored nor are
flags or aborts. A falling edge of
TxEN for transmit and a falling
edge of RxEN for receive is
in
the
Receive
Address
Recognition Registers or if the
address is an All call address.
6
RxEN
When low this bit will disable
the HDLC receiver. The
receiver will disable after the
rest of the packet presently
being received is finished. The
receiver internal clock is
disabled.
necessary
to
initialize
transparent mode. This will also
synchronize the data to the
transmit and receive channel
structure. Also, the transmitter
must be enabled through
When high the receiver will be
immediately enabled and will
begin searching for flags, Go-
aheads etc.
control register
transparent mode is entered.
1
before
5
TxEN
When low this bit will disable
the HDLC transmitter. The
transmitter will disable after the
completion of the packet
presently being transmitted.
The transmitter internal clock is
disabled.
0
FRUN
When high the HDLC TX and
RX are continuously enabled
providing the RxEN and TxEN
bits are set
Table 144 - HDLC Control register 1
(Page B & C, Address 13H)
When high the transmitter will
be immediately enabled and
will begin transmitting data, if
any, or go to a mark idle or
interframe time fill state.
4
EOP
Forms a tag on the next byte
written the TX FIFO, and when
set will indicate an end of
packet byte to the transmitter,
which will transmit an FCS
following
this
byte.
This
facilitates loading of multiple
packets into TX FIFO. Reset
automatically after a write to the
TX FIFO occurs.
3
FA
Forms a tag on the next byte
written to the TX FIFO, and
when set will indicate to the
transmitter that it should abort
the packet in which that byte is
being
transmitted.
Reset
automatically after a write to the
TX FIFO.
Table 144 - HDLC Control register 1
(Page B & C, Address 13H)
100
MITEL [ MITEL NETWORKS CORPORATION ]
