Advance Information
MT9074
Bit Name
Functional Description
Bit Name
---
Functional Description
Unused.
7-4
3
RSV These bits are reserved.
7
RxCLK Receive Clock. This bit represents
the receiver clock generated after
the RXEN control bit, but before
zero deletion is considered.
6-4 RFD2-0 These bits select the Rx FIFO full
status level:
RF RF RF
D2 D1 D0
Full Status Level
2
1
TxCLK Transmit Clock. This bit represents
the transmit clock generated after
the TXEN control bit, but before
zero insertion is considered.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
48
VCRC Valid CRC. This is the CRC
recognition status bit for the
receiver. Data is clocked into the
register and then this bit is
monitored to see if comparison was
successful (bit will be high).
64
80
96
112
128
0
VADDR Valid Address. This is the address
recognition status bit for the
receiver. Data is clocked into the
Address Recognition Register and
then this bit is monitored to see if
comparison was successful (bit will
be high).
3
---
Unused.
2-0 TFD2-0 These bits select the Tx HDLC FIFO
full status level:
TF TF TF
D2 D1 D0
Full Status Level
Table 153 - HDLC Test Status Register
(Page B & C, Address 1CH)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
48
64
80
96
112
128
Table 154 - HDLC Control Register 3
(Page B & C, Address 1DH)
105
MITEL [ MITEL NETWORKS CORPORATION ]
