MT90220
Address (Hex):
Direct access
048 - 04B
1 reg. per IMA Group.link. The RxClk signal must be active for correct register
operation
00
Reset Value (Hex):
Bit #
Type
Description
7:5
4:0
R
Unused. Read all 0’s.
R/W
UTOPIA PHY Address of IMA Group N.
Table 18 - UTOPIA Output Group Address Registers
Address (Hex):
Direct access
04C
1 register to enable the links in UNI mode. The RxClk signal must be active for
correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable UTOPIA PHY address of link 7. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 6. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 5. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 4. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 3. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 2. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address. UNI mode
Table 19 - UTOPIA Output Link PHY Enable Register
Address (Hex):
Direct access
04D
1 register to enable the IMA Groups. The RxClk signal must be active for correct
register operation
X0000000
Reset Value (Hex):
Bit #
Type
Description
7
R
Watch clock. This bit reflects the level present on the RX UTOPIA Clock pin when this
register is read.
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved, write 0 for normal operation.
Reset UTOPIA RX state machines when set to 1.
Reserved, write ’0’ for normal operation.
Enable UTOPIA PHY address of IMA Group 3. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 2. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address.
Table 20 - UTOPIA Output Group PHY Enable Register
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