MT90220
7.1 Utopia Register Description
Tables 12 to 22 describe the UTOPIA registers.
.
Address (Hex):
Direct access
000 - 007
1 register per link in UNI mode. The TxClk signal must be active for correct
register operation.
00
Reset Value (Hex):
Bit #
Type
Description
7:5
4:0
R
Unused. Read all 0’s.
R/W
UTOPIA PHY Address of Link N when in UNI.
Table 12- UTOPIA Input Link Address Registers
Address (Hex):
Direct access
008 - 00B
11 reg. per IMA Group. The TxClk signal must be active for correct register
operation
00
Reset Value (Hex):
Bit #
Type
Description
7:5
4:0
R
Unused. Read all 0’s.
R/W
UTOPIA PHY Address of IMA Group N.
Table 13 - UTOPIA Input Group Address Registers
Address (Hex):
Direct access
00C
1 register to enable the links in UNI mode. The TxClk signal must be active for
correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable UTOPIA PHY address of link 7. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 6. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 5. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 4. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 3. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 2. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address. UNI mode.
Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address. UNI mode.
Table 14 - UTOPIA Input Link PHY Enable Register
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