MT90220
Address (Hex):
Direct access
205
1 register to enable interrupts from IMA Groups. The RxClk signal must be
active for correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7-4
3
R
Unused. Read all 0’s.
R/W
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 3.
2
1
0
R/W
R/W
R/W
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 2.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 1.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 0.
Table 21 - RX UTOPIA IMA Group FIFO Overflow Enable Register
Address (Hex):
Direct access
221
1 register to enable interrupts from the links in UNI mode. The RxClk signal must
be active for correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7
R/W
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link7.
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 6.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 5.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 4.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link3.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 2.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 1.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 0.
Table 22 - RX UTOPIA Link FIFO Overflow Enable Register
44
MITEL [ MITEL NETWORKS CORPORATION ]
