MT90220
Pin Description (continued)
Pin #
Name
I/O
Description
74
Clk
I
System Clock (25 MHz nominal). In the MT90220, this clock is used for all
internal operations of the device.
76
54
Test1
Reset
I
I
Test1. This signal should be high for normal operation. The signal should be pulled
up for normal operation.
System Reset. This is an active low input signal. It causes the device to enter the
initial state. The Clk signal must be active to reset the internal registers.
72
71
TCK
TMS
I
I
JTAG Test Clock. It should be pulled down if not used
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. TMS has an
internal pull- up resistor.
70
68
69
TDI
TDO
TRST
I
JTAG Test Data Input.
O JTAG Test Data Output. Note: TDO is tristated by TMS pin.
I
TAG Test Reset (active low). Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan operation. Note: This pin has an
internal pull-down.
77
Test2
Test3
Test4
I
I
I
Test2. It should be pulled down for normal operation.
153
Test3. It should be pulled down for normal operation.
152
Test4. It should be pulled up for normal operation. NOT 5V TOLERANT
Notes:
1. Static memory stores the received cells. RAM is used for reordering the cells
2. These signals are used to transfer data between the MT90220 and the local processor
Pinout Summary
Type
Input
Output
I/O
Power
Ground
TX UTOPIA
RX UTOPIA
16
7
1
10
1
Microprocessor Interface
External Memory Interface
TX PCM Interface
RX PCM Interface
PLL Interface
14
8
8
22
8
16
24
4
2
1
Miscellaneous
10
Power
25
25
Ground
31
31
Total
208
75
45
32
7
MITEL [ MITEL NETWORKS CORPORATION ]
