MT90220
Pin Description
Pin #
Name
I/O
Description
ATM Input Port Signals (UTOPIA Transmit Interface)
22, 23, 24,
25, 26, 27,
28, 29
TxData
[7:0]
I
I
UTOPIA Transmit Data Bus. Byte-wide data driven from ATM LAYER device to
MT90220. Bit 7 is the MSB. All arriving data between the last byte of the previous
cell and the first byte of the following cell (indicated by the SOC signal) is ignored.
21
TxSOC
UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM
LAYER device when TxData[7:0] contains the first valid byte of the cell. After this
signal is high, the following 52 bytes should contain valid data. The MT90220 waits
for another TxSOC signal after reading a complete cell.
32
TxClk
I
I
UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the
MT90220 which synchronizes data transfers on TxData[7:0]. This signal is the
clock of the incoming data. Data is sampled on the rising edge of this signal.
30
20
TxEnb
TxClav
UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER
device during cycles when TxData contains valid cell data.
O UTOPIA Transmit Cell Available Indication Signal. For cell-level flow control in a
MPHY environment, TxClav is an active high tri-stateable signal from the MT90220
to the ATM LAYER device. A polled MT90220 drives TxClav only during each cycle
following one with its address on the TxAddr lines. The polled MT90220 asserts
TxClav high to indicate it can accept the transfer of a complete cell, otherwise it de-
asserts the signal.
34, 35, 36,
37, 38
TxAddr
[4:0]
I
Transmit Address.Five bit wide true data driven from the ATM to the PHY layer to
poll and select the appropriate MT90220. TxAddr[4] is the MSB. Each MT90220
keeps its addresses. The value for the Tx and Rx portions of the MT90220 can be
different
ATM Output Port Signals (UTOPIA Receive Interface) (see Note 1)
205, 206,
207, 2, 3,
4, 5, 6
RxData
[7:0]
O UTOPIA Receive Data Bus. Byte-wide data driven from MT90220 to ATM layer
device. RxData[7] is the MSB. To support multiple PHY configurations, RxData is
tri-stateable, enabled only in cycles following those with RxEnb asserted.
202
RxSOC
O UTOPIA Receive Start of Cell Signal. Active high asserted by the MT90220 when
RxData contains the first valid byte of a cell. To support multiple PHY
configurations, RxSOC is tri-stateable, enabled only in cycles following those with
RxEnb asserted.
15
17
RxClk
I
UTOPIA Receive Byte Clock. This signal is the clock of the outgoing data. Data
changes after the rising edge of this signal. The RxClk needs to be synchronized
with the system clock.
RxEnb
I
UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer
device to indicate that RxData[7:0] and RxSOC will be sampled at the end of the
next cycle. In multiple PHY configurations, RxEnb* is used to tri-state RxData and
RxSOC MT90220 outputs. In that case, RxData and RxSOC would be enabled only
in cycles following those with RxEnb asserted.
203
RxClav
O UTOPIA Receive Cell Available Indication Signal. For cell-level flow control in a
MPHY environment, RxClav is an active high tri-stateable signal from the MT90220
to ATM LAYER device. A polled MT90220 drives RxClav only during each cycle
following one with its address on the TxAddr lines. The polled MT90220 asserts
RxClav high to indicate it has a complete cell available for transfer to the ATM Layer
device, otherwise it de-asserts the signal.
4
MITEL [ MITEL NETWORKS CORPORATION ]
