MT90220
It also provides the content for received ICP cells
that contain some changes. The external T1 or E1
framers provide the low level status of the link. The
software integrates and responds to the various
events.
2.0 The ATM Transmit Path
The transmit path corresponds to a cell flow from the
ATM Layer towards the T1/E1 interface. The ATM cell
path on the transmit side starts at the UTOPIA L2
Interface. Once ATM cells are received at the
UTOPIA port, the device transfers these cells to the
transmit block.
1.2 Hardware Functions
The MT90220 circuitry implements the following
functions:
•
•
•
•
•
•
UTOPIA L2 Interface
The MT90220 provides ATM cell mapping and
transmission convergence blocks to transport ATM
cell payloads over eight flexible PCM Interface ports.
It uses these PCM Interface ports to communicate
with most off-the-shelf T1 or E1 framers.
verification of the incoming HEC (optional)
generation of a new HEC byte
transmit scheduler
generation of the TX IMA Data Cell Rate (IDCR)
generation and insertion of ICP cells, Filler
Cells and Stuff Cells in IMA mode
Each of the eight T1/E1 links can be assigned to
either an IMA Group or to a UNI link. A single T1/E1
link cannot be assigned to more than one IMA
Group.
•
generation of Idle Cells in UNI mode (from on-
chip copies of the cells)
•
•
flexible PCM formatting of the outgoing bytes
The functional block diagram at Figure 3 illustrates
the transmit function of the MT90220.
retrieval of ATM Cells from the incoming PCM
format
•
•
•
•
cell delineation
2.1 Cell_In_Control
retrieval and processing of ICP cells
synchronization of the IMA Frame
In general terms, the MT90220 transmit input port
has the following properties:
management of the internal re-sequencer RX
links (when active)
•
cell level handshaking complies with the ATM
Forum UTOPIA L2 Specification
•
•
•
extraction of the RX IDCR
•
•
behaves like a UTOPIA MPHY Device
verification of the delays between-links
each port can be enabled or disabled
independently
re-sequencing of ATM cells using external
Static RAM
•
•
generates and optionally verifies the HEC for
incoming cells
•
•
various performance monitoring counters
8-bit microprocessor interface (adaptable to
Intel or Motorola interfaces)
includes the ATM Forum polynomial when
generating the HEC (default option that can be
disabled)
•
•
either passes or removes incoming Idle cells
The MT90220 can be separated into four major
independent blocks and three support blocks.
either passes or removes incoming Unassigned
cells
•
•
provides a counter per UTOPIA port for the total
number of Idle and Unassigned cells (24 bits)
The four major independent blocks are:
•
•
•
•
the ATM Transmit Path
the ATM Receive Path
the PCM Interface
provides a counter per UTOPIA port for the total
number of cells with wrong incoming HEC (24
bits)
the UTOPIA Interface
•
provides a counter per UTOPIA port for the total
number of cells handled (24 bits)
The three support blocks are:
The input port can be enabled to remove (filter)
Unassigned or Idle cells. If Unassigned or Idle Cell
Filtering is enabled, the device checks for and
discards Unassigned or Idle cells. This function is
programmed in the UTOPIA Input Control register.
•
•
•
the Counter Block
the Interrupt Block
the Microprocessor Interface Block
Section 5 describes the UTOPIA Interface in more
detail.
9
MITEL [ MITEL NETWORKS CORPORATION ]
