MT90220
List of Tables
Table 46 - RX OIF Status Register...................................................................................................................... 53
Table 47 - RX OIF Counter Clear Command Register........................................................................................ 54
Table 48 - RX Load Values/Link Select Register ................................................................................................ 54
Table 49 - RX Link IMA ID Registers................................................................................................................... 54
Table 50 - RX ICP Cell Offset Register ............................................................................................................... 55
Table 51 - RX Link Frame Sequence Number Register...................................................................................... 55
Table 52 - RX Link SCCI Sequence Number Register........................................................................................ 55
Table 53 - RX Link OIF Counter Value Register ................................................................................................. 55
Table 54 - RX Link ID Number Register...............................................................................................................56
Table 55 - RX State Register............................................................................................................................... 56
Table 56 - RX ICP Cell Type RAM Register 1...................................................................................................... 57
Table 57 - ICP Cell Type RAM Register 2........................................................................................................... 58
Table 58 - RX ICP Cell Buffer Increment Read Pointer Register ........................................................................ 58
Table 59 - RX ICP Cell Level FIFO Status Register............................................................................................. 59
Table 60 - Test Mode Enable Register................................................................................................................. 59
Table 61 - SRAM Control Register...................................................................................................................... 60
Table 62 - RX External SRAM Read/Write Data ................................................................................................. 60
Table 63 - RX External SRAM Read/Write Address 0.......................................................................................... 60
Table 64 - RX External SRAM Read/Write Address 1......................................................................................... 60
Table 65 - RX External SRAM Read/Write Address 2......................................................................................... 60
Table 66 - RX External SRAM Control Register.................................................................................................. 62
Table 67 - Increment/Decrement Delay Control Register.................................................................................... 62
Table 68 - RX Delay Select Register................................................................................................................... 63
Table 69 - RX Delay MSB Register..................................................................................................................... 63
Table 70 - RX Delay LSB Register...................................................................................................................... 63
Table 71 - RX Delay Link Number Register ........................................................................................................ 63
Table 72 - RX Guardband/Delta Delay LSB Register........................................................................................... 64
Table 73 - RX Guardband/Delta Delay MSB Register.......................................................................................... 64
Table 74 - RX Maximum Operational Delay LSB Register................................................................................... 64
Table 75 - RX Maximum Operational Delay MSB Register.................................................................................. 64
Table 76 - RX Recombiner Registers.................................................................................................................. 65
Table 77 - RX Recombiner Delay Control Registers........................................................................................... 65
Table 78 - Enable Recombination Status............................................................................................................ 66
Table 79 - RX Reference Link Control Registers ................................................................................................ 66
Table 80 - RX IDCR Integration Registers .......................................................................................................... 66
Table 81 - TX PCM Link Control Register Number 2 ........................................................................................... 67
Table 82 - TX PCM Link Control Register Number 1 ........................................................................................... 68
Table 83 - RX PCM Link Control Register........................................................................................................... 69
Table 84 - PLL Reference Control Register ........................................................................................................ 70
Table 85 - Clock Activity Register........................................................................................................................ 71
Table 86 - RX Sync. Status Register................................................................................................................... 71
Table 87 - TX Sync. Status Register ................................................................................................................... 72
Table 88 - TX Clock Disabled Status................................................................................................................... 72
Table 89 - PLL REF Clock Disabled Status/Device Rev ..................................................................................... 72
Table 90 - Counter Byte Number 3 Register ....................................................................................................... 73
Table 91 - Counter Byte Number 2 Register ....................................................................................................... 73
Table 92 - Counter Byte Number 1 Register ....................................................................................................... 73
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MITEL [ MITEL NETWORKS CORPORATION ]
