MT90220
AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle
Characteristics
Sym
Min
Typ Max
Units
Test Conditions
1
2
3
4
5
UP_CS* set-up time to UP_R/W*
falling edge
t
1
ns
WS
Address and Data set up before
rising edge of UP_R/W
t
4
0
1
ns
ns
ns
SU
UP_AD, UP_CS and Data hold time
after UP_R/W* rising edge
t
t
ADH
CSH
UP_R/W low after rising edge or
UP_CS
UP_CS* high before next UP_CS
low
t
2
cycle
system
clock
WH
(see Note 1)
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
UP_OE
(READ)
t
csh
UP_CS
t
ws
UP_R/W
(WRITE)
t
wh
t
adh
UP_A[9:0]
UP_D[7:0]
ADDRESS VALID
t
su
DATA VALID
Figure 34 - CPU Interface Intel Timing - Write Access
97
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