MT90220
AC Electrical Characteristics - CPU Interface Timing - Read Cycle
Characteristics
Sym
Min Typ Max
Units
Test Conditions
1
2
R/W set-up time to UP_CS* falling edge
t
1
ns
ns
WS
Data valid after UP_OE*, UP_CS* or
UP_AD
t
28
ACC
3
4
5
UP_AD or UP_R/W* hold time after
UP_CS rising edge
t
0
3
ns
ns
ns
AH
CH
OE
Data hold time after rising edge of
UP_CS or UP_OE
t
t
UP_D low impedance after falling edge
of UP_OE
2.5
10
UP_OE
UP_CS
t
ch
t
ws
UP_R/W
t
ah
UP_AD[9:0]
Address Valid
t
oe
UP_D[7:0]
Data Valid
t
acc
t
ch
Figure 32 - CPU Interface Timing - Read Access
95
MITEL [ MITEL NETWORKS CORPORATION ]
