MT90220
AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle
Characteristics
Sym
Min
Typ Max
Units
Test Conditions
1
2
3
4
5
UP_R/W* set-up time to UP_CS*
falling edge
t
1
ns
WS
Address and Data set up before
rising edge of UP_CS*
t
4
0
1
ns
ns
ns
SU
UP_AD and Data hold time after
UP_CS rising edge
t
t
ADH
UP_R/W low after rising edge or
UP_CS
t
WH
UP_CS* high before next UP_CS
low
2
cycle
system
clock
CSH
(see Note 1)
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
UP_OE
UP_CS
t
t
csh
ws
t
t
wh
UP_R/W
adh
UP_AD[9:0]
Address Valid
Data Valid
UP_D[7:0]
t
su
Figure 33 - CPU Interface Motorola Timing - Write Access
96
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