MT90220
AC Electrical Characteristics - External Memory Interface Timing - Write Access
Item
Description
System Clock Period
Min
Typ
Max
t
t
t
t
t
t
t
t
t
t
38
40 ns
30 ns
46
CLK
Write Cycle Time
1 t
-10 ns
CLK
WC
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Enable* Setup Time
Write Enable* Hold Time
Data Setup Time
9 ns
AVWS
AVWH
CSWS
CSWH
WEWS
WEWH
WDS
3 ns
9 ns
3 ns
9 ns
3 ns
13 ns
Data Hold Time
3 ns
WDH
tclk
System Clock
tavwh
tavws
Address Valid
SR_A[18:0]
SR_CS
twc
tcsws
tcswh
twewh
SR_WE
twews
twdh
twds
SR_D[7:0]
Data Valid
Note: The SR_WE signal stays LOW until a READ cycle is to be performed
Figure 31 - External Memory Interface Timing - Write Cycle
93
MITEL [ MITEL NETWORKS CORPORATION ]
