MT90220
AC Electrical Characteristics - Utopia Interface Transmit Timing
Signal name
DIR
Item
Description
Min
Max
TxClk
A->P
TxClk frequency (nominal)
TxClk duty cycle
0
25 MHz
40%
-
60%
TxClk peak-to-peak jitter
TxClk rise/fall time
5%
-
4 ns
TxData[7:0], TxSOC, TxEnb*,
TxAddr[4:0]
A->P
A<-P
tT5
tT6
Input setup to TxClk
Input hold from TxClk
Input setup to TxClk
Input hold from TxClk
Signal valid
4 ns
0 ns
4 ns
0 ns
14 ns
14 ns
3 ns
-
-
-
-
-
-
-
TxClav[0]
tT7
tT8
tT9
tT10
tT11
Signal going high impedance
Signal going low impedance from
TxClk
tT12
Signal going high impedance from
TxClk
3 ns
-
AC Electrical Characteristics - Receive Timing
Signal name
DIR
Item
Description
Min
Max
RxClk
A->P
RxClk frequency (nominal)
RxClk duty cycle
0
25 MHz
40%
-
60%
RxClk peak-to-peak jitter
RxClk rise/fall time
5%
-
4 ns
RxEnb*, RxAddr[4:0]
A->P
tT5
tT6
tT7
tT8
Input setup to RxClk
Input hold from RxClk
Input setup to RxClk
Input hold from RxClk
Signal valid
4 ns
0 ns
4 ns
0 ns
18 ns
18 ns
3 ns
-
-
-
-
-
-
-
RxData[7:0], RxSOC, RxClav[0] A<-P
1
tT9
1
tT10
tT11
Signal going high impedance
Signal going low impedance from
RxClk
tT12
Signal going high impedance from
RxClk
3 ns
-
Note 1 - The RXCLK signal needs to be synchronous with the system clock refer to paragraph 5.2.
90
MITEL [ MITEL NETWORKS CORPORATION ]
