MT8977 ISO-CMOS
Preliminary Information
AC Electrical Characteristics† - Clock Timing (Figures 13 & 14)
‡
Characteristics
C2i Clock Period
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
tP20
tW20
400
200
50
488
244
600
300
ns
ns
ns
ns
ns
ns
µs
µs
C2i Clock Width High or Low
Frame Pulse Setup Time
Frame Pulse Hold Time
Frame Pulse Width
tP20 = 488 ns
tFPS
tFPH
50
tFPW
tFPOD
tTxSFH
tTxSFS
50
RxSF Output Delay
TxSF Hold Time
125
50 pF Load
0.5
0.5
124.5
124.5
TxSF Setup Time
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
F0i
Frame 12/24
Frame 2
Frame 1
RxSF
TxSF
C2i
ST-BUS
BIT CELLS
Bit
6
Bit
6
Bit
7
Bit
4
Bit
7
Bit
4
Bit
6
Bit
5
Bit
5
Bit
7
Bit
4
Bit
5
Figure 13 - Clock & Frame Alignment for ST-BUS Streams
tW20
t
P20
2.0V
C2i
0.8V
t
W20
t
t
t
FPS
FPH
FPS
2.0V
0.8V
t
FPW
F0i
t
FPOD
t
FPOD
2.0V
0.8V
RxSF
F0i
C2i
Frame 1
Frame 12/24
2.0V
0.8V
t
t
TxSF
TxSFH
2.4V
0.4V
TxSF
Figure 14 - Clock & Pulse Timing for ST-BUS Streams
4-118
MITEL [ MITEL NETWORKS CORPORATION ]
