Preliminary Information
ISO-CMOS MT8977
shows the MT8977 interfaced to a parallel bus
structure using two STPA‘s operating in modes 1 and
2.
Note: the configurations shown in Figures 11 and 12
using the MT8940/41 may not meet specific jitter
performance requirements. A more sophisticated
PLL or line interface unit with transmit jitter
attenuator may be required for applications designed
to meet specific standards.
The first STPA operating in mode 2 (MMS=0,
MS1=1, 24/32=0), routes data and/or voice
information between the parallel telecom bus and the
T1 or CEPT link via DSTi and DSTo. The second
STPA, operating in mode 1 (MMS = 1 ) provides
access from the signalling and link control bus to the
MT8977 status and control channels. All signalling
and link functions may be controlled easily through
the STPA transmit RAM’s Tx0, Tx1, while status
information is read at receive RAM Rx0. In addition,
interrupts can be set up to notify the system in case
of slips, loss of sync, alarms, violations, etc.
MT8980
MT8977
Tx
Line
Driver
TxA
TxB
Equa-
lizer
STi3
STo0
STi0
STo1
DSTi
DSTo
CSTi0
STo3
MH89761
CSTo
STi1
STo2
CSTi1
C4i
F0i
RxA
RxB
•
Line
Receiver
F0i
C2i
•
•
C1.5i
Micro
Processor
RxD
•
TxFDL
MT8940/41
TxFDLClk
TxSF
RxSF
E8Ko
MT8952
RxFDL
RxFDLClk
E1.5i
CDSTi
CKi
CDSTo
TxCEN
C2
Clock
Extractor
MT8940/41
CVb
1.544
MHz
12.355/12.352
MHz Osc.
RxCEN
F0i
C2o
F0b
D
Q
Q
D
Q
Q
•
16.388/16.384
MHz Osc.
C4b
C8Kb
C2
C2
Figure 11 - Typical ESF Configuration
4-115
MITEL [ MITEL NETWORKS CORPORATION ]
