MT8977 ISO-CMOS
Preliminary Information
50
Percentage Reframe Time Probability Versus Reframe Time
With Pseudo Random Data
D4
ESF
40
%
30
20
10
0
0
7
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Reframe Time (msec)
Figure 10 - Reframe Time
The out of sync threshhold can be changed from 2
out of 4 errors in F (or FPS) to 4 out of 12 errors in
output at E8Ko. The MT8940 uses this 8 kHz signal
to provide a phase locked 2.048 MHz clock for the
ST-BUS interface and a 1.544 MHz clock for the DS1
transmit side. Using the 8 kHz signal as a reference
for the MT8940/41 DPLL effectively filters out the
high frequency jitter in the extracted clock. Thus, the
C2 and C1.5 clocks generated by the MT8940/41 will
have significantly lower jitter than would be the case
if the extracted 1.5 MHz clock was used as a
reference directly.
T
F (or FPS). The average reframe time is 24 ms for
T
ESF mode, and 12ms for D3/D4 modes.
Figure 10 is a bar graph which shows the probability
of achieving frame synchronization at a specific time.
The chart shows the results for ESF mode with CRC
check, and D3/D4 modes of operation. The average
reframe time with random data is 24 ms for ESF, and
13 msec. D3/D4 modes. The probability of a reframe
time of 35 ms or less is 88% for ESF mode, and
An external line driver circuit is required in order to
interface the device to twisted pair cabling. The split
phase unipolar signals output by the MT8977 at TxA
and TxB are used by the line driver circuit to
generate a bipolar AMI signal. The line driver is
transformer coupled to an equalization circuit and
the DS1 line. Equalization of the transmitted signal
is required to meet the specifications for
crossconnect compatible equipment (see ANSI
T1.102 and AT & T Technical Advisory #34). On the
receive side the bipolar line signal is converted into
a unipolar format by the line receiver circuit. The
resulting split phase signals are input at the RxA and
RxB pins on the MT8977. The signals are combined
together to produce a composite return to zero signal
97% for D3/D4 modes.
In ESF mode it is
recommended that the CRC check be enabled
unless the line has a high error rate. With the CRC
check disabled the average reframe time is greater
because the framer must also check for mimics.
Applications
Figure 11 shows the external components that are
required in a typical ESF application. The MT8980 is
used to control and monitor the device as well as
switch data to DSTi and DSTo. The MT8952, the
HDLC protocol controller, is shown in this application
to illustrate how the data on the FDL could be used.
The digital phase-locked loop, the MT8940/41,
provides all the clocks necessary to make a
functional interface. The clock input to the MT8977
at E1.5i is extracted from the received data signal
with an external circuit. The E1.5i clock is internally
divided by 193 to obtain an 8 kHz clock which is
which is clocked into the device at RxD.
An
uncommitted nand gate in the MT8940/41 can be
used for this purpose.
The MT8977 can be interfaced to a high speed
parallel bus or to a microprocessor using the
MT8920B Parallel Access Circuit (STPA). Figure 11
4-114
MITEL [ MITEL NETWORKS CORPORATION ]
