MT8977 ISO-CMOS
Preliminary Information
AC Electrical Characteristics† - DS1 Link Timing (Figures 22 and 23)
‡
Parameters
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
Transmit FDL Setup Time
Transmit FDL Hold Time
Receive FDL Output Delay
Receive FDL Clock Delay
Transmit FDL Clock Delay
tDLS
tDLH
110
70
ns
ns
ns
tDLOD
tFRCD
tTFCD
0
50 pF Load
185
135
50 pF Load
50 pF Load
ns
† Timing is over recommended temperature & power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Frame 1
Frame 12/24
Frame 2
F0i
C2i
RxFDLClk
RxFDL
TxFDLClk
TxFDL
Figure 22 - Clock & Frame Alignment for RxFDL and TxFDL
2.0V
0.8V
C2i
2.0V
0.8V
Frame
tRFCD
2.0V
0.8V
RxFDLClk
RxFDL
tDLOD
2.0V
0.8V
tTFCD
2.0V
0.8V
TxFDLClk
TxFDL
tDLS
tDLH
2.0V
0.8V
Figure 23 - Facility Data Link Timing
4-122
MITEL [ MITEL NETWORKS CORPORATION ]
