MT8977 ISO-CMOS
Preliminary Information
Write
Pointer
13 CH
60 CH
2 CH
Wander Tolerance
386 Bit
Elastic
Store
15 CH
47 CH
-13 CH
28 CH
34 CH
Figure 8 - Elastic Buffer Functional Diagram (156 UI Wander Tolerance)
There is no loss of frame sync, multiframe sync or
any errors in the signalling bits when the device
performs a slip. The information on the FDL pins in
ESF or SLC-96 mode will, however, undergo slips at
the same time.
decrease over time. When this delay approaches
the minimum two channel threshold, the buffer will
perform a controlled slip, which will reset the internal
ST-BUS read pointers so that there is exactly 34
channels delay between the two pointers. This will
result in some ST-BUS channels containing
information output in the previous frame. Repetition
of up to one DS1 frame of information is possible.
Framing Algorithm
In ESF mode, the framer searches for a correct FPS
pattern. Figure 9 shows a state diagram of the
framing algorithm. The dotted lines show which
feature can be switched in and out depending upon
the operating mode of the device.
Conversely, if the data on the DS1 side is being
written into the buffer at a rate faster than it is being
read out on the ST-BUS side, the delay between the
DS1 frame and the ST-BUS frame will increase over
time. A controlled slip will be performed when the
throughput delay exceeds 60 ST-BUS channels.
This slip will reset the internal ST-BUS counters so
that there is a 28 channel delay between the DS1
write pointer and the ST-BUS read pointer, resulting
in loss of up to one frame of received DS1 data.
When the device is operating in the D3/D4 format,
the framer searches for the FT pattern, i.e., a
repeating 1010... pattern in a specific bit position
every alternate frame. It will synchronize to this
pattern
and
declare
valid terminal
frame
synchronization by clearing bit 0 in Master Status
Word 1. The device will subsequently initiate a
search for the FS pattern to locate the signalling
frames (see Table 4). When a correct FS pattern has
been located, bit 3 in Master Status Word 1 is
cleared indicating that the device has achieved
multiframe synchronization.
Figure 8 illustrates the relationship between the read
and write pointers of the receive elastic buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the writer
pointer a frame slip will occur, which will put the read
pointer 34 channels from the write pointer.
Conversely, if the read pointer moves more than 60
channels from the write pointer, a slip will occur,
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 ST-BUS channels peak (26 ST-BUS channels
peak-to-peak). This can be translated into a low
frequency jitter (wander) tolerance value, accounting
for the DS1 to ST-BUS rate conversion, as follows:
Note: the device will remain in terminal frame
synchronization even if no FS pattern can be located.
In D3/D4 format, when the CRC/MIMIC bit in Master
Control Word 1 is cleared, the device will not go into
synchronization if more than one bit position in the
frame has a repeating 1010.... pattern, i.e., if more
than one candidate for the terminal framing position
is located. The framer will continue to search until
only one terminal framing pattern candidate is
(1.544/2.048) X 26 X 8 = 156 UI pp.
4-112
MITEL [ MITEL NETWORKS CORPORATION ]
