CMOS MT8920B
AC Electrical Characteristics†- Mode 1 Parallel Bus Timing (see Fig. 14)
(V =5.0V ±5%,T =-40 to 85°C)
CC
A
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
††
1
2
3
4
Address to DS (CS) Low
t
0
ns
ns
ns
ns
ARDS
††
R/W to DS (CS) Low
t
20
RWDS
1,2
††
Load C
DS (CS) Low to DTACK Low
t
t
t
2*t
CLK
RDS
cwm
CLK
Load A, C =130pF, R =740Ω
Valid Data to DTACK Low (Read)
t
t
L
L
RD
cwm
-30
Load C, C =50pF
5
6
7
8
9
DS High to DTACK High
DS High to Data High Imped.(Read)
DS High to CS High
t
65
45
ns
ns
ns
ns
ns
L
DAR
Load A, C =130pF, R =740Ω
t
0
0
0
L
L
DHZ
CSH
t
Data Hold Time (Write)
t
DHT
Input Data Valid after DS
t
t
cwm
DST
-30
††
10 Address Hold Time
t
50
ns
ADHT
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C, V =5V, t
=244 ns, t =t =122 ns and are for design aid only: not guaranteed and not subject to production
CH CL
DD
CLK
testing.
††The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.
(1) t is equal to t or t whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having t =70ns
cwm
CH
CL
CHmin
or t
=70ns.
CLmin
(2) Worst case access when memory contention occurs.
A0 - A5
t
ADHT
†
CS (IACK )
t
ARDS
R/W
t
t
CSH
RWDS
DS
t
RDS
t
DAR
DTACK
D0 - D7
t
t
RD
DHZ
DATA OUT
t
t
DHT
DST
DATA IN
D0 - D7
Figure 14 - Mode 1 Parallel Bus Timing
† During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.
3-19
MITEL [ MITEL NETWORKS CORPORATION ]
