CMOS MT8920B
Connecting the STPA to a shared ST-BUS Line
a high impedance state at the output of U1,
corresponding to the selected channel.
The STPA’s STo0 and STo1 outputs cannot be
This method of three-state buffering permits output
control on a per-channel or per-bit basis.
directly forced into
a
high impedance state.
However, with some external logic, the STo0 output
can be buffered by a three-state device, controlled by
the STo1 output. This application is only possible if
the Tx1 RAM and associated STo1 output are not
required for some other purpose.
The ODE input is used to enable the ST-BUS outputs
after all ST-BUS devices are properly configured by
software.
This eliminates the possibility of
contention on the ST-BUS lines during the power-up
state.
Figure 13 shows an external buffer U1 controlled by
the STo1 output and an external Output Data Enable
(ODE) signal. When FF (hex) is written to the Tx1
RAM, the corresponding STo1 output channel goes
to logic high. This signal, AND-ed together with a
logic high at ODE, enables U1, resulting in the STo0
signal transparently passed to the output of U1.
When 00 (hex) is written to the Tx1 RAM, the STo1
output goes logic low. This disables U1, resulting in
74HC125
ST-BUS
STo0
U1
Parallel Port
MT8920B
74HC00
STo1
U2
ODE
ODE
STi0
STi1
STo0
STo1
MT8980
STi7
STo7
Parallel Port
Figure 13 - Connecting STPA to a Common ST-BUS Line
3-17
MITEL [ MITEL NETWORKS CORPORATION ]
