ACE9030
Data is accepted by the circuit on the rising edge of
Speed-up drive is active for the duration of the LATCHC
pulse that loads the A or A2 word and if it is required the pulse
will typically be hundreds of cycles of CL in duration.
In some applications the system performance can be
improvedbyholdingLATCHCatHIGHtominimiseclocknoise
on the synthesisers. LATCHC also controls Speed-up mode
and so to exit speed-up mode after a channel change the
LATCHC must be driven LOW and then a dummy command
can be added to get LATCHC back to HIGH. This dummy
command should be a non-functional word formed by setting
thelastfourbitsto1111asinfigure11;thevalueorthenumber
of the data bits before the four 1’s are of no significance so the
typical schemes are to send either a standard 24 bit message
ending 1111 or a special 4 bit only message of 1111 and in
both cases the LATCHC is kept HIGH until the next channel
change.
LATCHC.Programmabledividerratioswillbechangedattheir
next re-load, at up to a whole comparison period after the
LATCHC edge.
Normal channel changes require only word A but if it is
necessary to maintain exactly uniform loop dynamics the
parameter CN (see Main Synthesiser - Normal Mode) must
also change. This can be achieved by either sending a word
B for the CN parameter before word A for the frequency or
alternatively the extended command A2 can be used to
combinebothinonelongword. ThisA2modeisnotsupported
by the ACE9050 as it is not necessary for most cellular
terminals.
If Word B is reprogrammed, the new values do not
become effective until the next Word A is written. This
prevents any spurious conditions during a channel change.
The LG bit in Word D sets whether A or A2 mode is to be
used, 0 for A and 1 for A2.
The TEST bits in Word B must be set to 0000 for normal
operation and the first two bits in Word B should be set to 00
to be sure of compatibility with future variants.
Summary of Synthesiser Programming
BIT STRING
Range of values
3 - 4095
1 - 255
FUNCTION
N1
N2
NF
Main synthesiser down count; prescaler at lower modulus.
Main synthesiser up count; prescaler at higher modulus.
Main synthesiser fractional increment numerator.
This state must be selected in every Word B for normal operation.
TEST pin will be held LOW to screen adjacent PDA pin.
Other test modes are for use during chip manufacture only.
Main charge pump current scaling coefficient.
Integral charge pump speed-up mode multiplying factor.
Proportional charge pump speed-up mode exponent, giving x 2, x4, x 8
or x 16 current.
0 - 7
0000
TEST
CN
K
L
0 - 255
0 - 15
0 - 3
NA
NR
SM
DM
SA
DA
3 - 4095
8 - 4095
0 - 3
0, 1
0 - 3
0, 1
0, 1
0, 1
Auxiliary synthesiser VCO divider ratio.
Reference divider ratio.
Main synthesiser comparison frequency select.
Main synthesiser in standby mode if DM set HIGH.
Auxiliary synthesiser comparison frequency select.
Auxiliary synthesiser in standby mode if DA set HIGH.
Fractional-N denominator, 1/5’s when at “0” or 1/8’s when at “1”.
Control bus mode select - Word A if LOW or Word A2 if HIGH.
FMOD
LG
14
MITEL [ MITEL NETWORKS CORPORATION ]
