DATA SHEET
VSP 94x2A
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress 0Dh
D7-D6
D5-D3
CLMPVRB
[FP-RGB]
Clamping Value Red and Blue ADC
‘00’: 16 (B/R signal without sync)
‘01’: 80 (B/R signal with sync)
‘10’: 128 (U/V signal)
‘11’: (reserved)
FBLDEL
[FP-RGB]
Fast Blank Delay vs. RGB/YUV Input
granularity: 25 ns
‘000’: −50 ns delay
‘010’: no delay
‘110’: +100 ns delay
‘111’: (reserved)
D2-D1
D0
MIXOP
[FP-RGB]
Mixing Configuration
‘00’: enable Soft-Mix
‘01’: only RGB path visible
‘10’: only CVBS path visible
‘11’: (reserved)
FBLCONF
[FP-RGB]
Configuration of FBLACTIVE signal
‘0’: react after one clock (25 ns) active FBL input
‘1’: react after 5 clock (125 ns) active FBL input
Subaddress 0Eh
D7
YUVSEL
[FP-RGB]
YUV or RGB Input Selection
‘0’: YUV expected
‘1’: RGB expected
D6
SMOP
[FP-RGB]
Softmix Operation Mode
‘0’: dynamic
‘1’: static
D5
SKEWSEL
[FP-RGB]
SKEW Correction for RGB/YUV Channel
‘0’: SKEW correction enabled
‘1’: SKEW correction disabled (for PiP3, PiP4 only)
D4-D2
RBOFST
[FP-RGB]
Clamping Correction for R/B ADC
‘000’: 0 (R/B, no pedestal offset visible)
‘001’: 16
‘010’: 64 (R/B with sync, no pedestal offset visible)
‘011’: 80
‘100’: 127 (UV negative pedestal offset)
‘101’: 128 (UV)
‘110’: 129 (UV positive pedestal offset)
‘111’: (reserved)
D1-D0
GOFST
[FP-RGB]
Clamping correction for G ADC
‘00’: 0 (G/Y, no pedestal offset visible)
‘01’: 16
‘10’: 64 (G/Y with sync, no pedestal offset visible)
‘11’: 80
Micronas
Aug. 16, 2004; 6251-552-1DS
55
MICRONAS [ MICRONAS ]
