VSP 94x2A
DATA SHEET
2
3.1.4. I C Bus Command Description
Underlined values are initialized at power-on. Some
bits are intended to not be user adjustable. Mandatory
and recommended settings are available from Micro-
2
nas in a separate document (Application Note: I C
Settings).
2
Table 3–8: I C bus command description
Bit
Subaddress 00h
D7-D0 APPLIP8-1
Name
Description
Active Pixel Per Line
[FP-PRE]
Number of pixels to be stored in memory
Granularity: 2 pixel
‘000000000’: 0 pixel
‘101010101’: 682 pixel
‘111111111’: 1022 pixel
Subaddress 01h
D7
APPLIP0
Belongs to 00h
[FP-PRE]
D6-D0
HSCPRESC11-5
[FP-PRE]
Control Signal For HSCALE In Horizontal Pre-scaler
‘000000000000’: subsampling factor by scaler stage is 1
‘100000000000’: subsampling factor is 1.5 (720 pixel)
‘100101010110’: subsampling factor is 1.583 (682 pixel)
‘111111111111’: subsampling factor is 2 (540 pixel)
Subaddress 02h
D7-D3
HSCPRESC4-0
[FP-PRE]
Belongs to 01h
D2-D0
NAPPLIP9-7
[FP-PRE]
Not Active Pixel Per Line
Granularity: 2 clock cycles (~50 ns)
‘0000000000’: 0 clock cycles
‘0001001000’: 144 clock cycles (~7.2 µs)
‘1111111111’: 2046 clock cycles (~51 µs)
Subaddress 03h
D7
VDELF_EN
[FP-PRE]
Vertical pulse delay frontend
‘0’: no delay
‘1’: delayed
D6-D0
NAPPLIP6-0
[FP-PRE]
Belongs to 02h
Subaddress 04h
D7-D0 NALPFIP7-0
Not Active Lines Per Field (Input Processing)
‘000000000’: 0 lines
[FP-PRE]
‘000010110’: 22 lines
‘111111111’: 511 lines
52
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
