DATA SHEET
VSP 94x2A
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress 05h
D7
APENSEL
[FP-PRE]
Active Pixel Enable Select
0: count clock cycles (recommended for CVBS/RGB input)
1: count active pixels (recommended for ITU656 input)
D6
NALPFIP8
[FP-PRE]
Belongs to 04h
D5-D4
ALPFIP9-8
[FP-PRE]
Active Lines Per Field
‘0000000000’: no active line
‘0100100000’: 288 active lines
‘1111111111’: 1023 active lines
D3-D0
HDCPRESC
Horizontal Pre-Scaler Decimates By
‘0000’: 1
‘0001’: 2
‘0010’: 3
‘0011’: 4
‘0100’: 6
‘0101’: 8
‘0110’: 12
‘0111’: 16
‘1000’: 24
‘1001’: 32
Subaddress 06h
D7-D0
ALPFIP7-0
Belongs to 05h
Subaddress 07h
D7-D0
BLANDEL
Blanking signal delay
Delay in pixels from hsync to active edge of blank signal:
Blank_start=4*BLANDEL
‘00000000’: no delay
‘00000001’: 4 pixel delay
‘11111111’: 1020 pixel delay
Subaddress 08h
D7-D0
BLANLEN
Blanking signal length
Length in pixels from start of active blank signal:
Blank_length=4*BLANLEN
‘00000000’: no pixel
‘11110000’: 960 pixel
‘11111111’: 1020 pixel length
Micronas
Aug. 16, 2004; 6251-552-1DS
53
MICRONAS [ MICRONAS ]
