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VPX3226E 参数 Datasheet PDF下载

VPX3226E图片预览
型号: VPX3226E
PDF下载: 下载PDF文件 查看货源
内容描述: 视频像素解码器 [Video Pixel Decoders]
分类和应用: 解码器
文件页数/大小: 92 页 / 610 K
品牌: MICRONAS [ MICRONAS ]
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VPX 322xE  
ADVANCE INFORMATION  
2.7. Video Output Interface  
2.7.1. Output Formats  
The VPX supports the YC C 4:2:2 video format only.  
b
r
Contrary to the component processing stage running at  
a clock rate of 20.25 MHz, the output formatting stage  
(Fig. 2–17) receives the video samples at a pixel trans-  
port rate of 13.5 MHz. It supports 8 or 16-bit video for-  
mats with separate or embedded reference signals, pro-  
vides bus shuffling, and channels the output via one or  
both 8-bit ports. Data transfer is synchronous to the in-  
ternally generated 13.5 MHz pixel clock.  
Duringnormaloperation, allreferencesignalsareoutput  
separately. To provide a reduced video interface, the  
VPX offers two possibilities for encoding timing refer-  
ences into the video data stream: an ITU-R656 com-  
pliant output format with embedded timing reference  
headers and a second format with single timing control  
codes in the video stream. The active output format can  
be selected via FP-RAM 0x150 [format].  
The format of the output data depends on three parame-  
ters:  
2.7.1.1. YC C 4:2:2 with Separate Syncs/ITU-R601  
b
r
– the selected output format  
The default output format of the VPX is a synchronous  
16-bit YC C 4:2:2 data stream with separate reference  
S YC C 4:2:2, separate syncs  
b
r
b
r
S YC C 4:2:2, ITU-R656  
b
r
signals. Port A is used for luminance and Port B for chro-  
minance-information. Video data is compliant to ITU-  
R601. Bit[1:0] of FP-RAM 0x150 has to be set to 00. Fig-  
ure 2–18 shows the timing of the data ports and the  
reference signals in this mode.  
S YC C 4:2:2, embedded reference codes (BStream)  
b
r
– the number of active ports (A only, or both A and B)  
– clock speed (single, double, half).  
In 8-bit modes using only Port A for video data, Port B  
can be used as programmable output.  
Video  
Samples  
16  
8
8
8
8
8
8
8
8
Port A  
OE  
Port B  
PIXCLK  
LLC  
LLC2  
Clock  
Generation  
HREF  
VREF  
VACT  
Reference  
Signals  
Fig. 2–17: Output format stage  
Luminance  
(Port A)  
Y
1
Y
n–1  
Y
n
Chrominance  
(Port B)  
C
C
C
n
1
n–1  
VACT  
PIXCLK  
LLC  
Fig. 2–18: Detailed data output (single clock mode)  
18  
MICRONAS INTERMETALL  
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