VPX 322xE
ADVANCE INFORMATION
2.7.1.3. Embedded Timing Codes (BStream)
bus shuffler, luminance can be switched to port B and
chrominance to port A. In 8-bit double clock mode, shuf-
fling can be used to swap the Y and C components. It is
selected with FP-RAM 0x150.
In this mode, several event words are inserted into the
pixel stream for timing information. It is activated by set-
ting Bit[1:0] of FP-RAM 0x150 to 10. Each event word
consists of a chrominance code value containing the
phase of the color-multiplex followed by a luminance
code value signalling a specific event. The allowed con-
trol codes are listed in Table 2–5 and 2–6.
Table 2–5: Chrominance control codes
Chroma Value
Phase Information
FE
FF
C pixel
At the beginning and the end of each active video line,
timing reference codes (start of active video: SAV; end
of active video: EAV) are inserted with the beginning and
the end of VACT (see Fig. 2–23). Since VACT is sup-
pressed during blanked lines, video data and SAV/EAV
codes are present during active lines only. If raw/sliced
data should be output, VACT has to be enabled during
the VBI window with bit[2] of FP-RAM 0x138! In the case
of several windows per field, the length of the active data
stream per line can vary. Since the qualifiers for active
video (SAV/EAV) are independent of the other reference
codes, there is no influence on horizontal or vertical
syncs, and sync generation can be performed even with
several different windows. For full compliance with ap-
plications requiring data streams of a constant size, the
VPX provides a mode with programmable ‘video active’
signal VACT which can be selected via bit[2] of FP-RAM
0x140. The start and end positions of VACT relative to
HREF is determined by FP-RAM 0x151 and 0x152. The
delay of valid data relative to the leading edge of HREF
is calculated with the formulas given in Table 2–7 and
2–8. The result can be read in FP-RAM 0x10f (for win-
dow 1) and 0x11f (for window 2). Be aware that the larg-
est window defines the size of the needed memory. In
the case of 1140 raw VBI-samples and only 32 scaled
video samples, the graphics controller needs 570 words
for each line (the VBI-samples are multiplexed to lumi-
nance and chrominance paths).
r
C pixel
b
2.7.3. Output Multiplexer
During normal operation, a 16-bit YC C 4:2:2 data
b
r
stream is transferred synchronous to an internally gen-
erated PIXCLK at a rate of 13.5 MHz. Data can be
latched onto the falling edge of PIXCLK or onto the rising
edge of LLC during high PIXCLK. In the double clock
mode, luminance and chrominance data are multi-
plexed to 8 bit and transferred at the double clock fre-
quency of 27 MHz in the order C , Y, C , Y...; the first valid
chrominance value being a C sample. With shuffling
b
r
b
switched on, Y and C components are swapped. Data
can be latched with the rising edge of LLC or alternating
edges of PIXCLK. This mode is selected with bit[9] of
FP-RAM 0x154. All 8-bit modes use Port A only. In this
case, Port B can be used as input or activated as pro-
grammable output with bit[8] of FP-RAM 0x154. Bit[0–7]
determine the state of Port B (see Fig. 2–22).
to
7:0
controller
I2C 0xAB
The leading edge of HREF indicates the beginning of a
new video line. Depending on the type of the current line
(active or blanked), the corresponding horizontal refer-
ence code is inserted. For big window sizes, the leading
edge of HREF can arrive before the end of the active
data. In this case, hardware assures that the control
code for HREF is delayed and inserted after EAV only.
The VREF control code is inserted at the falling edge of
VREF. The state of HREF at this moment indicates the
current field type (HREF = 0: odd field; HREF = 1: even
field).
video data
8
=0
=1
8
Port
B[7:0]
ben
8
from
controller
7:0
FP-RAM 0x154 [outmux]
8
Fig. 2–22: Port B as input or programmable output port
In this mode, the words 0, 1, 254, and 255 are reserved
for data identifications. This is assured by limitation of
the video data.
2.7.4. Output Ports
The two 8-bit ports produce TTL level signals coded in
binary offset. The Ports can be tristated either via the
outputenablepin(OE)orviaI C register 0xF2. For more
2.7.2. Bus Shuffler
2
In the YC C 4:2:2 mode, the output of luminance data
is on port A and chrominance data on port B. With the
information, seesection2.18. “Enable/DisableofOutput
Signals”.
b
r
MICRONAS INTERMETALL
21
MICRONAS [ MICRONAS ]
