VPX 322xE
ADVANCE INFORMATION
Table 2–6: Luminance control codes
Luma Value
Video Event
VACT end
Video Event
Phase Information
01
02
03
04
05
06
last pixel was the last active pixel
next pixel is the first active pixel
begin of an active video line
begin of a blank line
refers to the last pixel
refers to the next pixel
refers to the current pixel
refers to the current pixel
refers to the current pixel
refers to the current pixel
VACT begin
HREF active line
HREF blank line
VREF even
begin of an even field
VREF odd
begin of an odd field
DATA
(Port A)
FFh
03h
FFh
02h
C
Y
C
Y
C
Y
C
Y
n
FEh
01h
b1
1
r1
2
bn–1
n–1
rn–1
VACT
HREF
PIXCLK
LLC
Fig. 2–23: Detailed data output with timing event codes (double clock mode)
2.8. Video Data Transfer
2.8.1. Single and Double Clock Mode
Data is transferred synchronous to the internally gener-
ated PIXCLK. The frequency of PIXCLK is 13.5 MHz.
The LLC signal is provided as an additional support for
both the 13.5 MHz and the 27 MHz double clock mode.
The LLC consists of a doubled PIXCLK signal (27 MHz)
for interface to external components which rely on the
Philips transfer protocols. In the single clock mode, data
can be latched onto the falling edge of PIXCLK or at the
rising edge of LLC during high PIXCLK. In double clock
mode, output data can be latched onto both clock edges
of PIXCLK or onto every rising edge of LLC. Combined
with the half-clock mode, the available transfer band-
widths at the ports are therefore 6.75 MHz, 13.5 MHz,
and 27.0 MHz.
The VPX supports a synchronous video interface. Video
data arrives to each line at the output in an uninterrupted
burst with a fixed transport rate of 13.5 MHz. The dura-
tionoftheburstismeasuredinclockperiodsofthetrans-
port clock and is equal to the number of pixels per output
line.
The data transfer is controlled via the signals PIXCLK,
VACT, and LLC. An additional clock signal LLC2 can be
switched to the TDO output pin to support different tim-
ings.
The VACT signal flags the presence of valid output data.
Fig. 2–24, 2–25, and 2–26 illustrate the relationship be-
tween the video port data, VACT, PIXCLK, and LLC.
Whenever a line of video data should be suppressed
(line dropping, switching between analog inputs), it is
done by suppression of VACT.
2.8.2. Clock Gating
To assure a fixed number of clock cycles per line, LLC
and LLC2 can be gated during horizontal blanking. This
mode is enabled when bit[7] of FP-RAM 0x153[refsig] is
set to 1. The start and stop timing is defined by
‘pval_start’ and ‘pval_stop’. Note that four additional
LLC cycles are inserted before and after to allow trans-
mission of SAV/EAV headers in ITU-R656 mode.
22
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
