VPX 322xE
ADVANCE INFORMATION
2.7.1.2. Embedded Reference Headers/ITU-R656
– For data within the VBI-window (e.g. sliced or raw tele-
text data), the user can select between limitation or re-
duction to 7-bit resolution with an additional LSB as-
suring odd parity (0 and 255 never occur). This option
can be selected via FP-RAM 0x150 [range].
The VPX supports an output format which is designed to
be compliant with the ITU-R656 recommendation. It is
activated by setting bit[1:0] of FP-RAM 0x150 to 01. The
16-bit video data must be multiplexed to 8 bit at the
double clock frequency (27 MHz) via FP-RAM 0x154,
bit[9] set to 1 (see also Section 2.7.3.: Output Multiplex-
er).
– The task bit can be used as a qualifier for VBI data. It
is set to zero during the programmed VBI window if
bit[11] in 0x150 is set.
– Ancillarydatablocksmaybelongerthan255bytes(for
raw data) and are transmitted without checksum. The
secondary data ID is used as high byte of the data
count (DC1; see Table 2–4).
In this mode, video samples are in the following order:
C , Y, C , Y, ... The data words 0 and 255 are protected
b
r
since they are used for identification of reference head-
ers. This is assured by limitation of the video data. Tim-
ing reference codes are inserted into the data stream at
the beginning and the end of each video line in the fol-
lowing way: A ‘Start of active video’-Header (SAV) is in-
serted before the first active video sample. The ‘end of
active video’-code (EAV) is inserted after the last active
video sample. They both contain information about the
field type and field blanking. The data words occurring
during the horizontal blanking interval between EAV and
SAV are filled with 0x10 for luminance and 0x80 for chro-
minance information. Table 2–3 shows the format of the
SAV and EAV header. Fig. 2–19 and 2–20 show stan-
dard ITU-R656 output waveforms.
– Ancillary data packets must not follow immediately af-
ter EAV or SAV.
– The total number of clock cycles per line, as well as
valid cycles between EAV and SAV may vary.
Table 2–3: Coding of the SAV/EAV-header
Bit No.
Word
MSB
7
LSB
0
6
1
0
0
F
5
1
0
0
V
4
1
0
0
H
3
1
2
1
1
1
First
1
0
0
T
1
Second
Third
0
0
0
0
Note that the following changes and extensions to the
ITU-R656 standard have been included to support hori-
zontal and vertical scaling, transmission of VBI-data,
etc.:
0
0
0
0
Fourth
P3
P2
P1
P0
– Both the length and the number of active video lines
varies with the selected window parameters. For com-
pliance with the ITU-R656 recommendation, a size of
720 samples per line must be selected for each win-
dow. To enable a constant line length even in the case
of different scaling values for the video windows, the
VPX provides a programmable ‘active video’ signal
(see section 2.9.4.).
T= 0 during VBI data (if enabled), else T = 1
F = 0 during field 1,
V = 0 during active lines
H = 0 in SAV,
F = 1 during field 2
V = 1 during vertical field blanking
H = 1 in EAV
The bits P0, P1, P2, and P3 are protection bits. Their
states are dependent on the states of F, V, and H. They
can be calculated using the following equations:
– During blanked lines, the VACT signal is suppressed.
VBI-lines can be marked as blanked or active, thus al-
lowingthechoiceofenabledorsuppressedVACTdur-
ing the VBI-window. The vertical field blanking flag (V)
in the SAV/EAV header is set to zero in any line with
enabled VACT signal (valid VBI or video lines).
P = H xor V xor T
3
P = H xor F xor T
2
P = V xor F xor T
1
P = H xor V xor F
0
The VPX also supports the transmission of VBI-data as
vertical ancillary data during blanked lines in the interval
starting with the end of the SAV and terminating with the
beginning of EAV. In this case, an additional header is in-
serted directly before the valid active data; thus, the
position of SAV and EAV depends on the settings for the
programmable VACT signal (see Fig. 2–21). These pa-
rameters will be checked and corrected if necessary to
assureanappropriatesizeofVACTforbothdataandan-
cillary header.
– During blanked lines SAV/EAV headers can be sup-
pressed in pairs with FP-RAM 0x150, bit[9]. To assure
vertical sync detection, some SAV/EAV headers are
inserted during field blanking.
– The flags F,V and H encoded in the SAV/EAV headers
change on SAV. With FP-RAM 0x150, bit[10] set to 1
they change on EAV. The programmed windows how-
ever are delayed by one line. Header suppression is
always applied for SAV/EAV pairs.
MICRONAS INTERMETALL
19
MICRONAS [ MICRONAS ]
